Alinx ZYNQ AC7Z035 User Manual page 18

ZYNQ
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PS system clock source
The ZYNQ chip provides a 33.333MHz clock input to the PS section via
the X4 crystal on the FPGA core board AC7Z035. The input of the clock is
connected to the pin of the PS_CLK_500 of the BANK500 of the ZYNQ chip.
The schematic diagram is shown in Figure 2-6-2:
Figure 6-2: Active crystal oscillator to the PS section
PS Clock Pin Assignment
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ZYNQ FPGA Development Board AC7Z035 User Manual
BANK
PS_CLCK
500
PS_CLCK_P
BANK
PS_CLCK_N
34
Bank111_CLK1_P
BANK
Bank111_CLK1_N
111
Figure 6-1: Clock source in the Core Board
Signal Name
PS_CLK
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Single-ended Clock
33.33 Mhz
Differential Clock
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Differential Clock
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ZYNQ Pin
B24
200 Mhz
200 Mhz