Alinx ZYNQ AC7Z035 User Manual page 10

Figure 3-1: The Schematic Part of DDR3 DRAM on the PS side
Figure 3-2: The Schematic Part of DDR3 DRAM on the PL side
PS side DDR3 DRAM pin assignment:
Signal Name
PS_DDR3_DQS0_P
PS_DDR3_DQS0_N
PS_DDR3_DQS1_P
PS_DDR3_DQS1_N
PS_DDR3_DQS2_P
PS_DDR3_DQS2_N
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ZYNQ FPGA Development Board AC7Z035 User Manual
ZYNQ Pin Name
PS_DDR_DQS_P0_502
PS_DDR_DQS_N0_502
PS_DDR_DQS_P1_502
PS_DDR_DQS_N1_502
PS_DDR_DQS_P2_502
PS_DDR_DQS_N2_502
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ZYNQ Pin Number
H24
G25
L24
L25
P25
R25