Instruction Description And Formats - ZiLOG Z8 PLUS User Manual

INSTRUCTION DESCRIPTION AND FORMATS

The following section lists each instruction set, and describes the:
Instruction Format
Operation performed
Flag Conditions
Examples of the code
The format for the instruction uses the following conventions:
NOTE: The bytes shown in the boxes are in machine code order. The ZiLOG assembler always requires
the format OPC, dst, src.
Address modes R or IR can be used to specify a 4-bit working register. In this format, the source or destina-
tion working-register operand is specified by adding 1110B (EH) to the High nibble of the operand. For
example, if working register R12 (CH) is the destination operand, then ECH is used as the destination operand
in the Op Code.
Address mode IRR can be used to specify a 4-bit working register Pair. In this format, the destination working
register Pair operand is specified by adding 1110B (EH) to the High nibble of the operand. For example, if
working register Pair RR12 (CH) is the destination operand, then ECH is used as the destination operand in
the Op Code.
4 Bits 8 Bits
E src
E
12 Bits 16 Bits
or E dst
dst
.75
P Â