Table of Contents
Advertisement
.75
P
Â
DECW
Decrement Word
Instruction Format:
DECW dst
Operation:
dst ← dst - 1
The contents of the destination (which must be an even address) operand are decremented by one. The desti-
nation operand can be a Register Pair or a working register Pair.
Flags:
When the instruction is executed, the flags are set as follows:
C:
The value set by the preceding instruction.
Z:
1 if the result is 0; otherwise, 0
S:
1 if bit 7 of the result is 1 (negative); otherwise, 0
V:
1 if arithmetic overflow occurs; otherwise, 0
D:
The value set by the preceding instruction.
H:
The value set by the preceding instruction.
Example:Register pair 30H and 31H contain the value 0AF2H. The statement leaves the value 0AF1H in
register pair 30H and 31H. The Z, V, and S flags are set to 0.
DECW 30H
Op Code: 80 30
Example: Working register R0 contains 30H. Register Pair 30H and 31H contain the value FAF3H. The
following statement leaves the value FAF2H in Register Pair 30H and 31H. The S flag is set, and the Z and
V flags are cleared.
DECW @R0
Op Code: 81 E0
OPC
dst
Address Mode
OPC (Hex)
80
81
dst
RR
IR
Advertisement
Table of Contents
Need help?
Do you have a question about the Z8 PLUS and is the answer not in the manual?
Questions and answers