Decimal Adjust - ZiLOG Z8 PLUS User Manual

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DA

Decimal Adjust

Instruction Format:
DA dst
Operation:
dst ← DA dst
The destination operand is adjusted to two 4-bit BCD digits following a binary addition or subtraction opera-
tion on BCD-encoded bytes. For addition (ADD and ADC) or subtraction (SUB and SBC), Table 3-14 indicates
the operation performed.
Table 3-16. DA Operation Reference
Flags Before DA
Prior
Instruction
C
ADD or ADC
0
0
0
0
1
0
0
1
1
SUB or SBC
0
0
1
1
Note: If the destination operand is not the result of a valid addition or subtraction of
OPC
dst
Result Before
H
D
[7...4]
0
0
0-9
0
0
0-8
1
0
1-9
0
0
A-F
0
0
0-2
0
0
9-F
1
0
A-F
0
0
0-2
1
0
0-3
0
1
0-9
1
1
0-8
0
1
7-F
1
1
6-F
OPC (Hex)
40
41
Adjustment
[3...0]
Added
0-9
00
A-F
06
0-3
06
0-9
60
0-9
60
A-F
66
0-3
66
A-F
66
0-3
66
0-9
00
6-F
FA
0-9
A0
6-F
9A
Address Mode
dst
R
IR
Result After
[7...4]
[3...0]
0-9
0-9
1-9
0-5
1-9
6-9
0-5
0-9
6-8
0-9
0-5
0-5
0-5
6-9
6-9
0-5
6-9
6-9
0-9
0-9
0-8
0-9
1-9
0-9
0-9
0-9
BCD
digits, the result is meaningless.
C Flag
After
0
0
0
1
1
1
1
1
1
0
0
1
1

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