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Instruction Format:
SRA dst
Operation:
C ← dst(0)
dst(0) ← dst(1)
dst(1) ← dst(2)
dst(2) ← dst(3)
dst(3) ← dst(4)
dst(4) ← dst(5)
dst(5) ← dst(6)
dst(6) ← dst(7)
dst(7) ← dst(7)
An arithmetic right shift by one bit position is performed on the destination operand. Bit 0 replaces the C flag.
The value of Bit 7 (the sign bit) is unchanged.Bit 6 becomes the same as the value of bit 7. The result is a
signed divide by two holding the half-bit remainder stored in the Carry (C) flag.
Flags:
When the instruction is executed, the flags are set as follows:
C:
1 if the value rotated from the least-significant bit (bit 0) position was 1.
Z:
1 if the result is 0; otherwise, 0.
S:
1 if bit 7 of the result is 1; otherwise, 0.
V:
0.
D:
The value set by the preceding instruction.
H:
The value set by the preceding instruction.
OPC
dst
D7 D6 D5 D4 D3 D2 D1 D0
Shift Right Arithmetic
Address Mode
OPC (Hex)
D0
D1
C
.75
P
Â
SRA
dst
R
IR
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