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PROCESSOR FLAGS
The Flag Register (FCH) informs the user of the processor'sbcurrent status. The flags and their bit positions
in the Flag Register are shown in Figure 3-1.
The Flag Register contains eight bits of status information which are set or cleared by CPU operations. Four
of the bits (C, V, Z and S) can be tested for use with conditional Jump instructions. Two flags (H and D) are
used for BCD arithmetic. The two remaining bits in the Flag Register are the watch-dog timer reset flag and
the stop mode recovery flag. Both of these flag bits may be tested and must be explicitly cleared by software.
As with bits in the other control registers, the Flag Register bits can be set or reset by instructions; however,
only those instructions that do not affect the flags as an outcome of the execution should be assigned a value.
Flag Register (FCH: Read/Write) R252 Flags
Bit
R/W
Reset
R = Read W = Write X = Indeterminate U = Unchanged
Bit
Bit/Field
Position
Carry
7
Flag (C)
Zero
6
Flag (Z)
Figure 3-1. Flag Register
7
6
R/W
R/W R/W
U
U
R/W
Value
Description
R/W
The Carry Flag is set to 1 whenever the result of an arithmetic
operation generates a carry out of or a borrow into the high
order bit 7. Otherwise, the Carry Flag is cleared to 0.
Following Rotate and Shift instructions, the Carry Flag
contains the last value shifted out of the specified register.
An instruction can set (I), reset(O), or complement the Carry
Flag.
The carry flag is not effected by RESET.
R/W
For arithmetic and logical operations, the Zero Flag is set to 1 if
the result is 0. Otherwise, the Zero Flag is cleared to 0.
If the result of testing bits in a register is 00H, the Zero Flag is
set to 1. Otherwise the Zero Flag is cleared to 0.
If the result of a Rotate or Shift operation is 00H, the Zero
Flag is set to 1.
The Zero Flag is not effected by a RESET command.
5
4
3
R/W
R/W
U
U
U
2
1
0
R/W
R/W
R/W
U
*
*
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