ZiLOG Z8 PLUS User Manual page 137

Figure 4-5. Interrupt Mask 2 Register
Interrupt Mask 2 Register–IMASK2 (F9H)
Bit 7
R/W R/W
Reset 0
R = Read W = Write X = Indeterminate U = Undefined/Undetermined
Bit
R/W
Position
7 R/W
6 R/W
5 R/W
4 R/W
3 R/W
2 R/W
1 R/W
0 R/W
6 5 4
R/W R/W R/W
0 0 0
Value Description
0
Disables IRQ14
1
Enables IRQ14
0
Disables IRQ13
1
Enables IRQ13
0
Disables IRQ12
1
Enables IRQ12
0
Disables IRQ11
1
Enables IRQ11
0
Disables IRQ10
1
Enables IRQ10
0
Disables IRQ9
1
Enables IRQ9
0
Disables IRQ8
1
Enables IRQ8
0 Disables IRQ7
1
Enables IRQ7
3 2 1
R/W R/W R/W
0 0 0
.75
P Â
0
R/W
0