Opcode Map - ZiLOG Z8 PLUS User Manual

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OP CODE MAP
0 1 2
DEC DEC ADD
0
R1 IR1 r1, r2
RLC RLC ADC
1
R1 IR1 r1, r2
INC INC SUB
2
R1 IR1 r1, r2
JP SRP SBC
3
IRR1 IM r1, r2
DA DA OR
4
R1 IR1 r1, r2
POP POP AND
5
R1 IR1 r1, r2
COM COM TCM
6
R1 IR1 r1, r2
PUSH PUSH TM
7
R2 IR2 r1, r2
DECW DECW
8
RR1 IR1
RL RL
9
R1 IR1
INCW INCW CP
A
RR1 IR1 r1, r2
CLR CLR XOR
B
R1 IR1 r1, r2
RRC RRC LDC
C
R1 IR1 r1, Irr2
SRA SRA LDC
D
R1 IR1 Irr1, r2
RR RR
E
R1 IR1
SWAP SWAP
F
R1 IR1
2
Notes:
P
LUS
All Z8 instructions execute in ten XTAL clock
cycles, (1 µS at 10 MHz).
Blank areas are reserved and execute as NOP.
* 2-byte instruction appears as a 3-byte instruction.
3 4 5
ADD ADD ADD ADD
r1, Ir2 R2, R1 IR2, R1 R1, IM
ADC ADC ADC ADC
r1, Ir2 R2, R1 IR2, R1 R1, IM
SUB SUB SUB SUB
r1, Ir2 R2, R1 IR2, R1 R1, IM
SBC SBC SBC SBC
r1, Ir2 R2, R1 IR2, R1 R1, IM
OR OR OR OR
r1, Ir2 R2, R1 IR2, R1 R1, IM
AND AND AND AND
r1, Ir2 R2, R1 IR2, R1 R1, IM
TCM TCM TCM TCM
r1, Ir2 R2, R1 IR2, R1 R1, IM
TM TM TM TM
r1, Ir2 R2, R1 IR2, R1 R1, IM
CP CP CP CP
r1, Ir2 R2, R1 IR2, R1 R1, IM
XOR XOR XOR XOR
r1, Ir2 R2, R1 IR2, R1 R1, IM
LDCI
Ir1, Irr2
LDCI * CALL
CALL
Irr1, Ir2 DA
IRR1
LD LD LD LD
r1, IR2 R2, R1 IR2, R1 R1, IM
LD LD
Ir1, r2 R2, IR1
3
BYTES PER INSTRUCTION
Legend:
R = 8-bit Addr
r = 4-bit Addr
R1 or r1 = Dst Addr
R2 or r2 = Src Addr
Sequence:
op code,
First Operand,
Second Operand
Figure 3-2. Op Code Map
LOWER NIBBLE (HEX)
6 7 8 9
ADD LD LD
IR1, IM r1, R2 r2, R1
ADC
IR1, IM
SUB
IR1, IM
SBC
IR1, IM
OR
IR1, IM
AND
IR1, IM
TCM
IR1, IM
TM
IR1, IM
CP
IR1, IM
XOR
IR1, IM
LD
r1,x,R2
LD
r2,x,R1
LD
IR1, IM
op code
A B C
DJNZ JR LD
r1, RA cc, RA r1, IM cc, DA
2
Lower op code Nibble
Upper
4
Nibble
CP
A
R2, R1
First Operand
D E F
JP INC
r1
WDT
STOP
HALT
DI
EI
RET
IRET
RCF
SCF
CCF
NOP
3 1
Mnemonic
Second Operand