ZiLOG Z8 PLUS User Manual page 140

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IREQ SOFTWARE INTERRUPT GENERATION
IREQ can be used to generate software interrupts by specifying IREQ as the destination of any instruction
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referencing the Z8
manner as hardware generated requests. In other words, the IMASK controls the enabling of each SWI.
To generate a SWI, the request bit in IREQ is set by the following statement:
OR IREQ,#NUMBER
The immediate data variable, NUMBER, has a 1 in the bit position corresponding to the required level of SWI.
For example, an SWI must be issued when an IREQ5 occurs. Bit 5 of NUMBER must have a value of 1.
OR IREQ, #00100000B
If the interrupt system is globally enabled, IREQ5 is enabled, and there are no higher priority requests
pending , control is transferred to the service routine pointed to by the IREQ5 vector.
NOTE: Note that software may modify the IREQ register at any time. Care should be taken when using
any instruction that modifies the IREQ register while interrupt sources are active. The software
writeback always takes precedence over the hardware. If a software writeback takes place on the
same cycle as an interrupt source tries to set an IREQ bit, the new interrupt is lost.
VECTORED PROCESSING
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Each Z8 interrupt level has its own vector. When an interrupt occurs, control passes to the service routine
pointed to by the interrupt's vector location in program memory. The sequence of events for vectored inter-
rupts is as follows:
PUSH the PC Low Byte on the Stack
PUSH the PC High Byte on the Stack
PUSH the FLAGS on the Stack
Disable Global Interrupts (bit 7 of IMASK)
Fetch the High Byte of the Vector
Fetch the Low Byte of the Vector
Branch to the Service Routine specified by Vector
Figure 4-8 and Figure 4-9 show vectored interrupt operation.
Standard Register File. These software interrupts (SWI) are controlled in the same