ZiLOG Z8 PLUS User Manual page 126

.75
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TM
Test Under Mask
Example: Working register R14 contains the value F3H (11110011B). Working register R5 contains CBH.
Register CBH contains 88H (10001000B) (bit 7 a bit 3 are tested if they are 0). The following statement
resets the Z flag to 0, because bit 7 in the destination operand is not a 0. The S flag is set to 1, and the V flag
is set to 0.
TM R14, @R5
Op Code: 73 E5
Example: Register D4H contains the value 08H (00001000B). Working register R0 contains the value 04H
(00000100B) (bit 2 is tested if it is 0). The statement sets the Z flag to 1, because bit 2 in the destination
operand is a 0. The S and V flags are set to 0.
TM D4H, R0
Op Code: 74 E0 D4
Example: Register DFH contains the value 00H (00000000B). Register 07H contains the value 1FH.
Register 1FH contains the value BDH (10111101B) (bit 7, bit 5, bit 4, bit 3, bit 2, and bit 0 are tested if
they are 0). The following statement sets the Z flag to 1, indicating the tested bits in the destination operand
are 0. The S is set to 1, and the V flag is set to 0.
TM DFH, @07H
Op Code: 75 07 DF
Example: Working register R13 contains the value F1H (11110001B). The following statement tests bit 1
of the destination operand for 0. The Z flag is set to 1, indicating bit 1 in the destination operand was 0. The
S and V flags are set to 0.
TM R13, #02H
Op Code: 76 ED, 02
Example: Register 5DH contains A0H. Register A0H contains 0FH (00001111B). The following statement
tests bit 4 of the register A0H for 0. The Z flag is set to 1, indicating bit 4 in the destination operand was 0.
The S and V flags are set to 0.
TM @5D, #10H
Op Code: 77 5D 10