Debug; Input/Output Summary - ST STR730-EVAL User Manual

UM0559
3.3

Debug

Figure 9.
Table 8.
Pin
4, 6, 8, 10, 12,
14, 16, 18, 20
1
2
3
Note: In order for hardware and JTAG RESET to be synchronized, (R3, R6, R5,C2,TR2, TR1)
have to be fitted, see
3.4

Input/output summary

Table 9.
Port
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P0.8
P0.9
P0.10
P0.11
P0.12
JTAG standard interface: CN1
19 17
20 18
JTAG interface pinout: CN1
Description Pin
Ground 5
VTref +5 V 7
Vsupply +5 V 9
notTRST 11
Figure 16: ARM JTAG interface on page
STR730-EVAL board input/output summary
Peripheral
LCD_D0
LCD_D1
LCD_D2
LCD_D3
LCD_D4
LCD_D5
LCD_D6
LCD_D7
LCD_RS
LCD_nE
LCD_RW
TP52
TP53
Debug-JTAG port
15 13 11 9 7 5
16 14 12 10 8 6
Description
TDI
TMS
TCK
RTCK (GROUND) 19
Alternate function
OCMPB2
OCMPA2
ICAPA2
ICAPB2
OCMPA5
OCMPB5
ICAPA5
ICAPB5
OCMPA6
OCMPB6
OCMPA7
OCMPB7
ICAPA3
Connectors
3 1
4 2
Pin Description
13 TD0
15 notReset
17 DBGRQS - pulled low
DBGACK - pulled low
25.
Interrupt
15/29