Wlan Interface - Quectel EC2 Series Design Manualline

3.7. WLAN Interface


Keep SDIO signals far away from other sensitive circuits/signals such as RF circuits, analog signals,
etc, as well as noisy signals such as clock and DC-DC signals, etc.

The total length of each SDIO signal trace should be less than 23 mm, and the difference between
them should be less than 1 mm.

The load capacitance for SD card signal traces should be less than 15 pF.
Keep the impedance of SDIO signal traces at 50 Ω 10 %, maintaining the integrity of the reference

plane. SD_CLK and SD_CMD should be surrounded with ground on the layer and adjacent ground
planes If limited by space, the SD_DATA0 to SD_DATA3 could be surrounded with ground together.
GND
GND
SDIO_CMD
SDIO_CMD
SDIO_CLK
SDIO_CLK
GND
GND
Figure 24: Overview of SDIO Signal Traces (FC20 TE-A 1st Layer)
EC2x&EG2x-G_Series_PCB_Design_Guideline
SDIO_DATA
SDIO_DATA
GND
GND
LTE Standard Module Series
EC2x&EG2x-G Series PCB Design Guideline
VDD_1V8
VDD_1V8
GND
SDIO_VDD
SDIO_VDD
GND
GND
GND
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