Quectel EC2 Series Design Manualline page 6

LTE Standard Module Series
EC2x&EG2x-G Series PCB Design Guideline
Figure Index
Figure 1: Overview of TE-A 1st Layer .......................................................................................................... 8
Figure 2: High-priority Signals to Be Designed (TE-A 1st Layer) ................................................................ 9
Figure 3: DC-DC Converter (EVB 4th Layer) and Module Interfaces On TE-A (EVB 1st Layer) .............. 10
Figure 4: VBAT Traces (TE-A 1st Layer) ................................................................................................... 11
Figure 5: Traces of VBAT with Capacitors (TE-A 4th Layer) ..................................................................... 11
Figure 6: Traces of VBAT with a TVS (TE-A 4th Layer) ............................................................................ 12
Figure 7: VBAT & Sensitive Signal Traces (TE-A 1st Layer)..................................................................... 12
Figure 8: PWRKEY and RESET_N Traces (TE-A 1st Layer) .................................................................... 13
Figure 9: PWRKEY and RESET_N Traces (TE-A 3rd Layer) ................................................................... 13
Figure 10: Overview of USB_DM/DP Signal Traces (EVB 1st Layer) ....................................................... 14
Figure 11: Overview of USB_DM/DP Signal Traces (EVB 3rd Layer) ...................................................... 15
Figure 12: Overview of USB_VBUS Signal Trace (EVB 1st Layer) .......................................................... 16
Figure 13: Overview of USB_VBUS Signal Trace (EVB 3rd Layer) .......................................................... 16
Figure 14: Overview of SGMII Signal Traces (TE-A 1st Layer) ................................................................. 17
Figure 15: Overview of SGMII Signal Traces (TE-A 3rd Layer) ................................................................ 18
Figure 16: Recommended PCB Layout of SGMII Interface (TE-A 4th Layer) ........................................... 19
Figure 17: Recommended Reference PCB Layout of SGMII Interface (EVB 3rd Layer) .......................... 19
Figure 18: Layout of Recommended 4.7 μH Inductor, GND and Traces of AR8033 (EVB 1st Layer) ..... 20
Figure 19: Overview of PCM Signal Traces (TE-A 3rd Layer)................................................................... 21
Figure 20: Overview of Codec ALC5616 (EVB 1st Layer) ......................................................................... 22
Figure 21: Overview of Analog Audio Signal Traces (EVB 1st Layer) ...................................................... 23
Figure 22: Overview of SD Card Signal Traces (EVB 1st Layer) ............................................................. 24
Figure 23: Overview of SD Card Signal Traces (EVB 3rd Layer) ............................................................. 24
Figure 24: Overview of SDIO Signal Traces (FC20 TE-A 1st Layer) ....................................................... 25
Figure 25: Overview of SDIO Signal Traces (FC20 TE-A 3rd Layer) ....................................................... 26
Figure 26: Overview of (U)SIM Signal Traces (EVB 1st Layer) ................................................................ 27
Figure 27: Overview of (U)SIM Signal Traces (EVB 2nd Layer) ............................................................... 27
Figure 28: Overview of ADC Signal Traces (EVB 3rd Layer) ................................................................... 28
Figure 29: Overview of GPIO Signal Traces (TE-A without Copper Pouring) ........................................... 29
Figure 30: PCB Structure of Microstrip Waveguide ................................................................................... 30
Figure 31: PCB Structure of Coplanar Waveguide .................................................................................... 31
Figure 32: Microstrip Design on a 2-layer PCB ......................................................................................... 32
Figure 33: Coplanar Waveguide Design on a 2-layer PCB ....................................................................... 32
Figure 34: Coplanar Waveguide Design on a 4-layer PCB (Layer 3 as Reference Ground) .................... 33
Figure 35: Coplanar Waveguide Design on a 4-layer PCB (Layer 4 as Reference Ground) .................... 33
Figure 36: Overview of RF Traces (EVB 1st Layer).................................................................................. 34
Figure 37: Overview of RF Traces (EVB 1st and 2nd Layers).................................................................. 34
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