Ethernet Phy; Sgmii Interface - Quectel EC2 Series Design Manualline

3.4. Ethernet PHY

3.4.1. SGMII Interface


Signal traces of SGMII_MCLK, SGMII_MDATA, EPHY_RST_N and EPHY_INT_N should be
surrounded with ground.

The spacing between SGMII_TX_M/SGMII_TX_P/SGMII_RX_M/SGMII_RX_P lines should be at
least 3 times wider than the traces, and that between the SGMII signal trace and other signal traces
should also be at least 3 times wider than SGMII traces.

Keep the maximum length of the SGMII signal traces less than 10 inches and the difference between
signals of the differential pairs (SGMII_TX_P and SGMII_TX_M, SGMII_RX_P and SGMII_RX_M)
less than 20 mil.
 The differential impedance of SGMII signal traces is 100 Ω ± 10 %, and the reference ground of the
area should be complete.

The series capacitors for SGMII_TX_M/SGMII_TX_P should be close to PHY component, while the
series capacitors for SGMII_RX_M/SGMII_RX_P should be close to the two pins.
Figure 14: Overview of SGMII Signal Traces (TE-A 1st Layer)
EC2x&EG2x-G_Series_PCB_Design_Guideline
LTE Standard Module Series
EC2x&EG2x-G Series PCB Design Guideline
interface
SGMII
17 / 37