Fd-Can; Ethernet; Memories; Table 11. Can Related Jumpers And Solder Bridges - ST STM32H743I-EVAL User Manual

Hardware layout and configuration
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FD-CAN

The STM32H743I-EVAL Evaluation board supports one channel of the Flexible Data Rate
CAN (FD-CAN) communication bus, based on the 3.3 V CAN transceiver.
The standby signal on the FD-CAN transceiver is controlled by PD3 of the STM32H743XI.
Other FD-CAN signals are shared with USB OTG1 FS signals.

Table 11. CAN related jumpers and solder bridges

Jumper
CAN terminal resistor is enabled when JP1 is fitted.
JP1
Default setting: Not fitted
PA12 is connected with FDCAN TX signal when JP2 is fitted.
JP2
Default setting: Not fitted
PA11 is connected with FDCAN RX signal when SB50 is closed.
SB50
Default setting: Open

Ethernet

The STM32H743I-EVAL Evaluation board supports 10M/100M Ethernet communication by
a PHY LAN8742A (U5) and integrated RJ45 connector (CN1). Ethernet PHY is connected
to STM32H743XI through the RMII interface.
A 50-M reference clock can be generated by PHY with 25-M crystal or with 25-M MCO from
STM32H743XI. These two resources can be selected by setting jumper JP5 as shown in
Table 12.
Jumper
50M RMII reference clock is generated by an external crystal X3 when JP5 is set as
shown to the right: (Default setting)
JP5
50M RMII reference clock is generated by MCO at PA8 when JP5 is set as shown to
the right:

Memories

An 8M x 32-bit SDRAM is connected to the SDRAM bank1 of the FMC interface of the
STM32H743XI microcontroller.
A 1Mx16-bit SRAM is connected to the NOR/PSRAM2 bank1 of the FMC interface and both
8-bit and 16-bit accesses are allowed by BLN0 and BLN1, connected to BLE and BHE of
SRAM respectively.
Description

Table 12. Ethernet related jumpers

Description
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UM2198