Sdram Memory" On Page - Analog Devices EZ-KIT Lite Manual

SDRAM Memory
/* tRP=21ns min
/* tRCD=20ns min
/* tREF=64ms/4K rows ->
/* -> SDRDIV= (100MHz*64ms/4096) – 13 = 1549 = 0x60D cycles */
/* Note: If you change any clock, you have to change all settings
for best performance */
init_21161_SDRAM_controller:
ustat1=dm(WAIT);
bit clr ustat1 0x000FFFFF;
dm(WAIT)=ustat1;
ustat1=0x60D;
dm(SDRDIV)=ustat1;
ustat1=0x040146A2;
dm(SDCTL)=ustat1;
init_21161_SDRAM_controller.end:
rts;
When you are in a VisualDSP++ session connected to the ADSP-21161N
EZ-KIT Lite board, the SDRAM registers are configured automatically
through the debugger each time the processor is reset. Clearing the Auto
configure external memory check box on the Target Options dialog box,
which is accessible through the Settings pull-down menu, disables this
feature. For more information see
1-8
-> SDTRP=3*2=6
-> SDTRCD=2*2=4
/* clear MS0 wait state count */
/* refresh rate */
/* mask in SDRAM settings */
"Target Options" on page
ADSP-21161N EZ-KIT Lite Evaluation System Manual
[active delay]
[CAS-to-RAS delay] */
1-13.
*/
*/