Analog Devices EZ-KIT Lite Manual page 43

which the core operates is determined by the location of the clock mode
jumper ( ) as described
JP21
runs at 100 MHz.
External Port
The External Port (EP) of the processor connects to a 512K x 8-bit flash
memory. The flash memory connects to the boot memory select (
pin and the memory select 1 (
memory to be used to boot the processor as well as to store information
during normal operation.
The external memory interface also connects to 1M x 48-bit SDRAM
memory. The SDRAM memory connects to the memory select 0 (
pin. Refer to "SDRAM Disable Jumper (JP1)" on page 2-5
tion on how to configure the width of the SDRAM. Refer to
Memory" on page 1-6
Some of the address, data, and control signals are available externally via
two off-board connectors. The EP connectors' pinout (
found in Appendix B,
Host Processor Interface (HPI)
The Host Port Interface (HPI) signals are brought to an unpopulated
off-board connector (
application. The pinout of the host port connector can be found in
Appendix B, "Schematics".
SPORT Audio Interface
and
SPORT0 SPORT2
stereo jack and four RCA mono jacks facilitate an audio input, while a
3.5 mm stereo jack and eight RCA mono jacks facilitate an audio output.
ADSP-21161N EZ-KIT Lite Evaluation System Manual
EZ-KIT Lite Hardware Reference
on page 2-11. By default, the processor core
) pin. The connection allows the flash
~MS1
for a summary of the processor's memory map.
"Schematics".
). This allows the HPI to interface with a user
P9
are connected to the AD1836 codec (
)
~BMS
)
~MS0
for informa-
"SDRAM
and ) can be
P9 P10
). A 3.5 mm
U10
2-3