Analog Devices EZ-KIT Lite Manual page 31

Table 1-1. EZ-KIT Lite Evaluation Board Memory Map
Start Address
0x0000 0000
0x0002 0000
0x0002 8000
Internal
Memory 0x0004 0000
0x0005 0000
0x0008 0000
0x000A 0000
0x0010 0000
0x0020 0000
External
0x0400 0000
Memory
0x0800 0000
0x0C00 0000
Listing 1-1. ADSP-21161N EZ-KIT Lite – SDRAM Settings
/* SDRAM Controller Setup for the ADSP-21161N EZ-KIT Lite
/* Assumes SDRAM part# Micron MT48LC16M16A1-7SE (1Mx16-bit,
2 banks)
/* Default Factory Hardware settings (rev2.3)
/* LK_CFG[1:0]= 10,~CLDBL=1
/* CLKIN=25 MHz, => CCLK=100 MHz
/* 3 SDRAMs by 16 bits wide total = 3x(1Mx16-bit) = 1M x 48-bit */
/* Mapped to MS0 addresses 0x00200000-0x002fffff */
/* Estimated SDCLK 50 MHz => SDCKR=0
/* Settings must be double counted for SDCKR-bit=0, except CAS
Latency) */
/* 50 MHz min @ CL=2 -> SDCL=2 [CAS Latency]
/* tRAS=42ns min
ADSP-21161N EZ-KIT Lite Evaluation System Manual
End Address Content
IOP Registers (Internal)
0x0001 FFFF
Block 0 Long Word Addressing
0x0002 1FFF
Block 1 Long Word Addressing
0x0002 9FFF
Block 0 Normal Word Addressing
0x0004 3FFF
Block 1 Normal Word Addressing
0x0005 3FFF
Block 0 Short Word Addressing
0x0008 7FFF
Block 1 Short Word Addressing
0x000A 7FFF
Multi-processor Memory Space
0x001F FFFF
External Memory Space Bank 0 (SDRAM)
0x002F FFFF
External Memory Space Bank 1 (FLASH)
0x047F FFFF
External Memory Space Bank 2
0x0BFF FFFF
External Memory Space Bank 3
0x0FFF FFFF
-> SDTRAS=5*2=10 [precharge delay]
Using EZ-KIT Lite
*/
*/
*/
*/
*/
*/
*/
*/
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