Using Sdram Memory" On Page - Analog Devices ADSP-21161N EZ-KIT Lite Manual

Using SDRAM Memory
/* Mapped to MS0 addresses 0x00200000-0x002fffff */
/* Estimated SDCLK 50 MHz => SDCKR=0
/* Settings must be double counted for SDCKR-bit=0, except CAS
Latency) */
/* 50 MHz min @ CL=2 -> SDCL=2 [CAS Latency]
/* tRAS=42ns min
/* tRP=21ns min
/* tRCD=20ns min
/* tREF=64ms/4K rows ->
/* -> SDRDIV= (100MHz*64ms/4096) – 13 = 1549 = 0x60D cycles */
/* Note: If you change any clock, you have to change all settings
for best performance */
init_21161_SDRAM_controller:
ustat1=dm(WAIT);
bit clr ustat1 0x000FFFFF;
dm(WAIT)=ustat1;
ustat1=0x60D;
dm(SDRDIV)=ustat1;
ustat1=0x040146A2;
dm(SDCTL)=ustat1;
init_21161_SDRAM_controller.end:
rts;
The SDRAM registers are configured automatically through the debugger.
Checking the Manual External Mem configuration box in the Target
Options dialog box, as shown in
automatic setting.
2-4
-> SDTRAS=5*2=10 [precharge delay]
-> SDTRP=3*2=6
-> SDTRCD=2*2=4
/* clear MS0 wait state count */
/* refresh rate */
/* mask in SDRAM settings */
Figure 2-1 on page
ADSP-21161N EZ-KIT Lite Evaluation System Manual
*/
[active delay]
[CAS-to-RAS delay] */
2-10, disables the
*/
*/
*/
*/