Other Options; Core Hang Conditions - Analog Devices EZ-KIT Lite Manual

Other Options

Table 1-6 describes other available target options.
Table 1-6. Other Target Options
Option
Verify all writes to target
memory
Reset cycle counters on
run
Auto configure external
memory

Core Hang Conditions

Certain peripheral devices, such as host ports, DMA, and link ports, can
hold off the execution of processor instructions. This is known as a hung
condition and commonly occurs when reading from an empty port or
writing to a full port. If an attempt to halt the processor is made during
one of these conditions, the EZ-KIT Lite may encounter a core hang.
Normally, a core hang can be cleared by the board using a special
clear/abort bit. However, there are cases in which it is desirable or possible
not to clear the core hang. Sometimes it is desirable to wait for the core
hang to clear itself, such as when waiting for a host processor to read or
write data. In other cases, it is not possible to clear the core hang, and a
processor reset must occur to continue the debugging session.
Table 1-7 describes the EZ-KIT Lite's core hang operations.
ADSP-21161N EZ-KIT Lite Evaluation System Manual
Description
Validates all memory writes to the processor. After each write, a read
is performed and the values are checked for a matching condition.
Enable this option during initial program development to locate
and fix initial build problems (such as attempting to load data into
non-existent memory).
Clear this option to increase performance while loading executable
files since VisualDSP++ does not perform the extra reads that are
required to verify each write.
Resets the cycle count registers to zero before a Run command is
issued. Select this option to count the number of cycles executed
between breakpoints in a program.
Enables the automatic configuration of the SDRAM registers (done
through the debugger).
Using EZ-KIT Lite
1-15