Page 1: About This Document
Intended audience This reference manual is addressed to embedded hardware and software developers. Reference manual Please read the Important Notice and Warnings at the end of this document 002-34474 Rev. *C www.infineon.com page 1 2024-05-28...
Page 2: Table Of Contents
PSoC™ 4000T MCU architecture Table of contents Table of contents About this document Scope and purpose ................1 Intended audience .
Page 3 PSoC™ 4000T MCU architecture Table of contents Systick timer ................29 Debug .
Page 4 PSoC™ 4000T MCU architecture Table of contents Block diagram ................54 Clock sources .
Page 5 PSoC™ 4000T MCU architecture Table of contents Reset system ..............76 14.1 Reset sources .
Page 6 PSoC™ 4000T MCU architecture Table of contents Timer, counter, and PWM (TCPWM) ..........140 16.1 Features .
Page 7 PSoC™ 4000T MCU architecture Table of contents 19.5.1 Silicon ID ................196 19.5.2 Configure clock .
Page 8: Section A: Overview
PSoC™ 4000T MCU architecture Section A: Overview This section encompasses the following chapters: • “Introduction” on page 9 • “Getting started” on page 14 • “Document construction” on page 16 Reference manual 002-34474 Rev. *C 2024-05-28...
Page 9: Introduction
HMI solution for harsh environments. PSoC™ 4000T is a microcontroller with standard communication, timing peripherals and Infineon’ fifth- generation CAPSENSE™ and MULTI-SENSE HMI technology purpose built for varieties of low power applications including wearable, hearable and smart connected IoT products that needs low power operation and improved performance to enable next generation of user experience.
Page 10: Features
– Autonomous channel scanning in without assistance from MCU core for low power optimization with active touch detection and tracking – Advanced proximity sensing with directivity with machine learning based algorithms – Infineon-supplied software middleware makes capacitive sensing design easy – Automatic hardware tuning (SmartSense) •...
Page 11: Cpu System
PSoC™ 4000T MCU architecture Introduction CPU system 1.3.1 Processor The heart of the PSoC™ is a 32-bit Cortex®-M0+ CPU core running up to 48 MHz. It is optimized for low-power operation with extensive clock gating. It uses 16-bit instructions and executes a subset of the Thumb-2 instruction set.
Page 12: Power System
PSoC™ 4000T MCU architecture Introduction 1.4.2 Power system The device operates with a single external supply in the range 1.71 V to 5.5 V. It provides multiple power supply domains – V to power the digital section, and V for noise isolation of the analog section. V and V should be shorted externally.
Page 13: Special Function Peripherals
PSoC™ 4000T MCU architecture Introduction Special function peripherals 1.5.1 CAPSENSE™ PSoC™ 4000T device features Fifth-generation CAPSENSE™ and MULTI-SENSE technology. The key features of Fifth-generation CAPSENSE™ sensing are as follows: • All-new ratio-metric sensing architecture in multi-sense converter (MSCLP) provides best-in-class signal-to- noise ratio (SNR) (>5:1) and liquid tolerance for capacitive sensing.
Page 14: Getting Started
Development ecosystem 2.1.1 PSoC™ 4 MCU resources Infineon® provides a wealth of data at www.infineon.com to help you select the right PSoC™ device and quickly and effectively integrate it into your design. The following is an abbreviated, hyperlinked list of resources for PSoC™...
Page 15: Modustoolbox™ Software
Getting started 2.1.2 ModusToolbox™ software ModusToolbox™ software is Infineon®' comprehensive collection of multi-platform tools and software libraries that enable an immersive development experience for creating converged MCU and wireless systems. It is: • Comprehensive - it has the resources you need •...
Page 16: Document Construction
PSoC™ 4000T MCU architecture Document construction Document construction This document includes the following sections: • “CPU system” on page 22 • “System resources subsystem (SRSS)” on page 43 • “Digital system” on page 78 • “Analog system” on page 180 •...
Page 17: Units Of Measure
PSoC™ 4000T MCU architecture Document construction Units of measure Table 3-1. Units of measure Abbreviation Unit of measure bits per second °C degrees celsius decibels femtofarads Hertz kilo, 1000 kilo, 2^10 1024 bytes, or approximately one thousand bytes Kbit 1024 bits kilohertz (32.000) k...
Page 18: Acronyms
PSoC™ 4000T MCU architecture Document construction Acronyms Table 3-2. Acronyms Acronym Definition ABUS analog output bus alternating current analog-to-digital converter advanced encryption standard  AMBA (advanced microcontroller bus architecture) high-performance bus, an Arm data transfer application programming interface APOR analog power-on reset broadcast clock brownout detect bill of materials...
Page 19 PSoC™ 4000T MCU architecture Document construction Table 3-2. Acronyms (continued) Acronym Definition electronic code book external crystal oscillator EEPROM electrically erasable programmable read only memory EMIF external memory interface feedback FIFO first in first out full scale range GPIO general purpose I/O host-controller interface HFCLK high-frequency clock...
Page 20 PSoC™ 4000T MCU architecture Document construction Table 3-2. Acronyms (continued) Acronym Definition memory protection unit most significant bit most significant byte multi sense converter main stack pointer non-maskable interrupt NVIC nested vectored interrupt controller output feedback program counter printed circuit board program counter high program counter low power down...
Page 21 PSoC™ 4000T MCU architecture Document construction Table 3-2. Acronyms (continued) Acronym Definition single-ended zero secure hash algorithm signal-to-noise ratio start of frame start of instruction stack pointer sequential phase detector serial peripheral interconnect SPIM serial peripheral interconnect master SPIS serial peripheral interconnect slave SRAM static random-access memory SROM...
Page 22: Section B: Cpu System
PSoC™ 4000T MCU architecture Section B: CPU system This section encompasses the following chapters: • “Cortex®-M0+ CPU” on page 23 • “Interrupts” on page 30 • “Device security” on page 41 Top level architecture CPU system block diagram CPU Subsystem SWD/TC ...
Page 23: Cortex®-M0+ Cpu
PSoC™ 4000T MCU architecture Cortex®-M0+ CPU Cortex®-M0+ CPU The PSoC™ 4 Arm® Cortex®-M0+ core is a 32-bit CPU optimized for low-power operation. It has an efficient two- stage pipeline, a fixed 4-GB memory map, and supports the ARMv6-M a subset of the Thumb-2 instruction set. The Cortex®-M0+ also features a single-cycle 32-bit multiply instruction and low-latency interrupt handling.
Page 24: How It Works
PSoC™ 4000T MCU architecture Cortex®-M0+ CPU How it works The Cortex®-M0+ is a 32-bit processor with a 32-bit data path, 32-bit registers, and a 32-bit memory interface. It supports most 16-bit instructions in the Thumb instruction set and some 32-bit instructions in the Thumb-2 instruction set.
Page 25 PSoC™ 4000T MCU architecture Cortex®-M0+ CPU Table 4-2. Cortex®-M0+ registers (continued) Name Type Reset value Description The program counter (PC) is register R15. It contains the current program address. On reset, the processor loads the PC with the value PC (R15) [0x00000004] from address 0x00000004.
Page 26: Operating Modes
PSoC™ 4000T MCU architecture Cortex®-M0+ CPU Table 4-3. Cortex®-M0+ PSR bit assignments (continued) Name Usage Register 23 – 6 – – Reserved 5 – 0 IPSR Exception number of current ISR: 0 = thread mode 1 = reserved 2 = NMI 3 = HardFault 4 –...
Page 27: Instruction Set
PSoC™ 4000T MCU architecture Cortex®-M0+ CPU Instruction set The Cortex®-M0+ implements a version of the Thumb instruction set, as Table 4-4 shows. For details, see the Cortex®-M0+ devices generic user guide. An instruction operand can be an Arm® register, a constant, or another instruction-specific parameter. Instructions act on the operands and often store the result in a destination register.
Page 28 PSoC™ 4000T MCU architecture Cortex®-M0+ CPU Table 4-4. Thumb instruction set (continued) Mnemonic Brief description MVNS Bit wise NOT No operation ORRS Logical OR Pop registers from stack PUSH Push registers onto stack Byte-reverse word REV16 Byte-reverse packed half-words REVSH Byte-reverse signed half-word RORS Rotate right...
Page 29: Address Alignment
PSoC™ 4000T MCU architecture Cortex®-M0+ CPU 4.7.1 Address alignment An aligned access is an operation where a word-aligned address is used for a word or multiple word access, or where a half-word-aligned address is used for a half-word access. Byte accesses are always aligned. No support is provided for unaligned accesses on the Cortex®-M0+ processor.
Page 30: Interrupts
PSoC™ 4000T MCU architecture Interrupts Interrupts The Arm® Cortex®-M0+ (CM0+) CPU in PSoC™ 4 supports interrupts and exceptions. Interrupts refer to those events generated by peripherals external to the CPU such as timers, serial communication block, and port pin signals. Exceptions refer to those events that are generated by the CPU such as memory access faults and internal system timer events.
Page 31: Interrupts And Exceptions - Operation
PSoC™ 4000T MCU architecture Interrupts Interrupts and exceptions - Operation 5.3.1 Interrupt/exception handling The following sequence of events occurs when an interrupt or exception event is triggered: 1. Assuming that all the interrupt signals are initially low (idle or inactive state) and the processor is executing the main code, a rising edge on any one of the interrupt lines is registered by the NVIC.
Page 32: Level And Pulse Interrupts
PSoC™ 4000T MCU architecture Interrupts 5.3.2 Level and pulse interrupts NVIC supports both level and pulse signals on the interrupt lines (IRQ0 to IRQ12). The classification of an interrupt as level or pulse is based on the interrupt source. IRQn IRQn is still high Execution main...
Page 33: Exception Vector Table
PSoC™ 4000T MCU architecture Interrupts 5.3.3 Exception vector table The exception vector table (Table 5-1), stores the entry point addresses for all exception handlers. The CPU fetches the appropriate address based on the exception number. Table 5-1. Exception vector table Exception Exception Exception...
Page 34: Exception Sources
(SROM). The boot code and other data in SROM memory are programmed by Infineon®, and are not read/write accessible to external users. After completing the SROM boot sequence, the CPU code execution jumps to flash memory. Flash memory address 0x00000004 (Exception#1 in Table 5-1) stores the location of the startup code in flash memory.
Page 35: Supervisor Call (Svcall) Exception
PSoC™ 4000T MCU architecture Interrupts 5.4.4 Supervisor Call (SVCall) exception Supervisor Call (SVCall) is an always-enabled exception caused when the CPU executes the SVC instruction as part of the application code. Application software uses the SVC instruction to make a call to an underlying operating system and provide a service.
Page 36: Interrupt Sources
PSoC™ 4000T MCU architecture Interrupts Interrupt Sources PSoC™ 4 supports up to 13 interrupts (IRQ0 to IRQ12 or exception numbers 16 – 28) from peripherals. The source of each interrupt is listed in Table 5-2. PSoC™ 4 provides flexible sourcing options for each interrupt line. The interrupts include standard interrupts from the on-chip peripherals such as TCPWM and serial communication block.
Page 37: Enabling And Disabling Interrupts
PSoC™ 4000T MCU architecture Interrupts The priority of the 13 interrupts (IRQ0 to IRQ12) can be configured by writing to the Interrupt Priority registers (CM0P_IPR). This is a group of 32-bit registers with each register storing the priority values of four interrupts, as given in Table 5-3.
Page 38: Exception States
PSoC™ 4000T MCU architecture Interrupts Exception states Each exception can be in one of the following states. Table 5-5. Exception states Exception state Meaning The exception is not active or pending. Either the exception is disabled or the enabled Inactive exception has not been triggered.
Page 39: Stack Usage For Exceptions
PSoC™ 4000T MCU architecture Interrupts Setting the pending bit when the same bit is already set results in only one execution of the ISR. The pending bit can be updated regardless of whether the corresponding interrupt is enabled. If the interrupt is not enabled, the interrupt line will not move to the pending state until it is enabled by writing to the CM0P_ISER register.
Page 40: Exceptions - Initialization And Configuration
PSoC™ 4000T MCU architecture Interrupts 5.11 Exceptions – Initialization and configuration This section covers the different steps involved in initializing and configuring exceptions in PSoC™ 4. 1. Configuring the Exception Vector Table Location: The first step in using exceptions is to configure the vector table location as required –...
Page 41: Device Security
PSoC™ 4000T MCU architecture Device security Device security PSoC™ 4 offers a number of options for protecting user designs from unauthorized access or copying. Disabling debug features and enabling flash protection provide a high level of security. The debug circuits are enabled by default and can only be disabled in firmware. If disabled, the only way to re- enable them is to erase the entire device, clear flash protection, and reprogram the device with new firmware that enables debugging.
Page 42: How It Works
PSoC™ 4000T MCU architecture Device security How it works 6.2.1 Device security The CPU operates in normal user mode or in privileged mode, and the device operates in one of four protection modes: BOOT, OPEN, PROTECTED, and KILL. Each mode provides specific capabilities for the CPU software and debug.
Page 43: Section C: System Resources Subsystem (Srss)
PSoC™ 4000T MCU architecture Section C: System resources subsystem (SRSS) This section encompasses the following chapters: • “I/O system” on page 44 • “Clocking system” on page 54 • “Power supply and monitoring” on page 61 • “Power modes” on page 65 •...
Page 44: O System
PSoC™ 4000T MCU architecture I/O system I/O system This chapter explains the PSoC™ 4 MCU I/O system, its features, architecture, operating modes, and interrupts. The I/O system provides the interface between the CPU core and peripheral components to the outside world. The flexibility of PSoC™...
Page 45: I/O Cell Architecture
PSoC™ 4000T MCU architecture I/O system GPIO pins are connected to I/O cells. These cells are equipped with an input buffer for the digital input, providing high input impedance and a driver for the digital output signals. The digital peripherals connect to the I/O cells via the high-speed I/O matrix (HSIOM).
Page 46: Digital Input Buffer
PSoC™ 4000T MCU architecture I/O system 7.3.1 Digital input buffer The digital input buffer provides a high-impedance buffer for the external digital input. The buffer is enabled and disabled by the INP_DIS bit of the Port Configuration Register 2 (GPIO_PRTx_PC2, where x is the port number). The input buffer is connected to the HSIOM for routing to the CPU port registers and selected peripherals.
Page 47: Drive Mode
PSoC™ 4000T MCU architecture I/O system 7.3.2.1 Drive modes Each I/O is individually configurable into one of eight drive modes using the Port Configuration register, GPIO_PRTx_PC. Table 7-2 lists the drive modes. Figure 7-3 is a simplified output driver diagram that shows the pin view based on each of the eight drive modes.
Page 48: Slew Rate Control
PSoC™ 4000T MCU architecture I/O system • High-impedance analog High-impedance analog mode is the default reset state; both output driver and digital input buffer are turned off. This state prevents an external voltage from causing a current to flow into the digital input buffer. This drive mode is recommended for pins that are floating or that support an analog voltage.
Page 49: High-Speed I/O Matrix
PSoC™ 4000T MCU architecture I/O system High-speed I/O matrix The high-speed I/O matrix (HSIOM) is a set of high-speed multiplexers that route internal CPU and peripheral signals to and from GPIOs. HSIOM allows GPIOs to be shared with multiple functions and multiplexes the pin connection to a user-selected peripheral.
Page 50: Behavior In Low-Power Modes
PSoC™ 4000T MCU architecture I/O system Behavior in low-power modes Table 7-4 shows the status of GPIOs in low-power modes. Table 7-4. GPIO in low-power modes Low-power mode Status GPIOs are active and can be driven by peripherals such as CAPSENSE™, TCPWM and SCBs, which can operate in sleep mode.
Page 51 PSoC™ 4000T MCU architecture I/O system Besides the pins, an edge detector is also present at the glitch filter output. This filter can be used on one of the pins of a port. The pin is selected by writing to the FLT_SEL field of the GPIO_PRTx_INTR_CFG register as shown Table 7-6.
Page 52: Peripheral Connections
PSoC™ 4000T MCU architecture I/O system Once, the IO port(s) is determined, the IO port's INTR register is read to determine the IO pad(s) in the IO port that caused the interrupt. Table 7-8. Interrupt cause PORT_INT Description 00001b Interrupt caused by Port 0 00010b Interrupt caused by Port 1 00100b...
Page 53: Serial Communication Block (Scb)
PSoC™ 4000T MCU architecture I/O system 7.7.3 Serial communication block (SCB) SCB blocks can be configured as UART, I C, and SPI have dedicated connections to the I/O pins. See the device datasheet for details on these dedicated pins. When UART and SPI mode are used, the SCB controls the digital output buffer drive mode for the input pin in order to keep the pin in the high-impedance state.
Page 54: Clocking System
PSoC™ 4000T MCU architecture Clocking system Clocking system The PSoC™ 4 clock system includes these clock resources: • Two internal clock sources: – 24-48 MHz internal main oscillator (IMO) – 20-80 kHz (typically 40-kHz) internal low-speed oscillator (ILO) • One external clock source (EXTCLK) generated using a signal from an I/O pin •...
Page 55: Clock Sources
PSoC™ 4000T MCU architecture Clocking system Clock sources 8.2.1 Internal main oscillator (IMO) The IMO is an accurate, high-speed internal (crystal-less) oscillator that is available as the main clock source during Active and Sleep modes. It is the default clock source for the device. Its frequency can be changed in 4-MHz steps between 24 MHz and 48 MHz.
Page 56: Startup Behavior
PSoC™ 4000T MCU architecture Clocking system Start Change the IMO frequency to 24 MHz by writing to the CLK_IMO_SELECT register Read the course trim from SFLASH and load into the CLK_IMO_TRIM1 register Clear fine trim – CLK_IMO_TRIM2 register Read the temperature compensation settings from SFLASH and load into the TCTRIM field of the...
Page 57: Internal Low-Speed Oscillator (Ilo)
PSoC™ 4000T MCU architecture Clocking system 8.2.2 Internal low-speed oscillator (ILO) The ILO operates with no external components and outputs a stable clock at 40-kHz nominal. The ILO is relatively low power and low accuracy. Refer to the device datasheet for ILO specifications.
Page 58: Peripheral Clock Divider Configuration
PSoC™ 4000T MCU architecture Clocking system Table 8-3. SYSCLK prescaler divide value bits SYSCLK_DIV Name Description SYSCLK prescaler divide value 0: SYSCLK = HFCLK SYSCLK_DIV[3:0] 1: SYSCLK = HFCLK/2 2: SYSCLK = HFCLK/4 3: SYSCLK = HFCLK/8 8.3.4 Peripheral clock divider configuration PSoC™...
Page 59 PSoC™ 4000T MCU architecture Clocking system Table 8-6. Fractional peripheral clock divider configuration register PERI_DIV_24_5_CTL Bits Name Description Divider enabled. Hardware sets this field to ‘1’ as a result of an ENABLE command EN_x and to ‘0’ as a result of a DISABLE command. Fractional division by (FRAC5_DIV/32).
Page 60: Low-Power Mode Operation
PSoC™ 4000T MCU architecture Clocking system Table 8-8. Programmable clock control register - PERI_PCLK_CTLx Bits Name Description Specifies one of the dividers of the divider type specified by SEL_TYPE. If SEL_DIV is ‘4’ and SEL_TYPE is “1”, then the fifth (zero being first) 16-bit clock divider will be routed to SEL_DIV the mux output for peripheral clock_x.
Page 61: Power Supply And Monitoring
PSoC™ 4000T MCU architecture Power supply and monitoring Power supply and monitoring PSoC™ 4 is capable of operating from a 1.71 V to 5.5 V externally supplied voltage. This is supported through one of the two following operating ranges: • 2.0 V to 5.50 V supply input to the internal regulators •...
Page 62: Power Supply Scenarios
PSoC™ 4000T MCU architecture Power supply and monitoring The supply voltage range is 1.71 V to 5.5 V with all functions and circuits operating in that range. The device allows two distinct modes of power supply operation: unregulated external supply and regulated external supply modes.
Page 63: Direct 1.71 V To 1.89 V Supply
PSoC™ 4000T MCU architecture Power supply and monitoring 9.2.2 Direct 1.71 V to 1.89 V supply In direct supply configuration, V and V are shorted together and connected to a 1.71-V to 1.89-V supply. This regulated supply should be connected to the device, as shown in Figure 9-3.
Page 64: Voltage Monitoring
PSoC™ 4000T MCU architecture Power supply and monitoring 9.3.1.2 Deep-Sleep regulator This regulator supplies the circuits that remain powered in Deep-Sleep mode, such as the ILO and SCB (I C/SPI), and low-power comparator. The Deep-Sleep regulator is available in all power modes. In Active and Sleep power modes, the main output of this regulator is connected to the output of the Active digital regulator (V Voltage monitoring The voltage monitoring system includes power-on reset (POR) and brownout detection (BOD).
Page 65: Power Modes
PSoC™ 4000T MCU architecture Power modes Power modes The PSoC™ 4 provides three power modes, intended to minimize the average power consumption for a given application. The power modes, in the order of decreasing power consumption, are: • Active • Sleep •...
Page 66: Active Mode
PSoC™ 4000T MCU architecture Power modes Table 10-1 illustrates the power modes offered by PSoC™ 4. Table 10-1. PSoC™ 4 power modes Power Wakeup Wakeup Available Description Entry condition Active clocks mode sources action regulators Wakeup from other power Primary mode of operation; modes, internal All regulators Active...
Page 67: Deep Sleep Mode
PSoC™ 4000T MCU architecture Power modes 10.3 Deep Sleep mode In Deep Sleep mode, the CPU, SRAM, and high-speed logic are in retention. The high-frequency clocks, including HFCLK and SYSCLK, are disabled. Optionally, the internal low-frequency oscillator (ILO, 40 kHz) remains on and low-frequency peripherals continue to operate.
Page 68: Low-Power Mode Entry And Exit
PSoC™ 4000T MCU architecture Power modes Table 10-3. Wakeup sources Power mode Wakeup source Wakeup action Any enabled interrupt source Interrupt Sleep Any reset source Reset GPIO interrupt Interrupt I2C address match Interrupt Deep-Sleep Watchdog timer Interrupt/Reset CAPSENSE™ Interrupt Note: In addition to the wakeup sources mentioned in Table 10-3, external reset (XRES) and brownout reset...
Page 69: Chip Operational Modes
PSoC™ 4000T MCU architecture Chip operational modes Chip operational modes PSoC™ 4 is capable of executing firmware in four different modes. These modes dictate execution from different locations in flash and ROM, with different levels of hardware privileges. Only three of these modes are used in end-applications;...
Page 70: Watchdog Timer (Wdt)
PSoC™ 4000T MCU architecture Watchdog timer (WDT) Watchdog timer (WDT) The WDT is used to automatically reset the device in the event of an unexpected firmware execution path or a brownout that compromises the CPU functionality. The WDT runs from ILO. The timer interrupt must be serviced periodically in firmware to avoid a reset.
Page 71: Enabling And Disabling Wdt
PSoC™ 4000T MCU architecture Watchdog timer (WDT) When the WDT is used to protect against system crashes, clearing the WDT interrupt bit to reset the watchdog must be done from a portion of the code that is not directly associated with the WDT interrupt. Otherwise, even if the main function of the firmware crashes or is in an endless loop, the WDT interrupt vector can still be intact and feed the WDT periodically.
Page 72: Wdt Reset Mode
PSoC™ 4000T MCU architecture Watchdog timer (WDT) 12.3.3 WDT reset mode The RESET_WDT bit in the RES_CAUSE register indicates the reset generated by the WDT. This bit remains set until cleared or until a power-on reset (POR), brownout reset (BOD), or external reset (XRES) occurs. All other resets leave this bit untouched.
Page 73: Trigger Multiplexer Block
PSoC™ 4000T MCU architecture Trigger multiplexer block Trigger multiplexer block Select peripherals in the PSoC™ 4 MCU are interconnected using trigger signals. Trigger signals are means by which peripherals denote an occurrence of an event or a state. These triggers are used as means to affect or initiate some action in other peripherals.
Page 74: Trigger Multiplexer Group
PSoC™ 4000T MCU architecture Trigger multiplexer block 13.2.1 Trigger multiplexer group The trigger multiplexer block is implemented using several trigger multiplexers. A trigger multiplexer selects a signal from a set of trigger output signals from different peripheral blocks to route it to a specific trigger input of another peripheral block.
Page 75: Software Triggers
PSoC™ 4000T MCU architecture Trigger multiplexer block Trigger Mux Group 0 1 [0] SW Input CPUSS.zero TCPWM(16-bit) 6 [1:6] Tr_overflow[0:1] Tr_compare_match[0:1] TCPWM(16-bit) Tr_underflow[0:1] Tr_in[7:13] 2 [7:8] SCB.tr_i2c_scl_filtered [0:1] Figure 13-3. PSoC™ 4000T MCU trigger multiplexer block architecture 13.2.2 Software triggers All input and output signals to a trigger multiplexer can be triggered from software.
Page 76: Reset System
PSoC™ 4000T MCU architecture Reset system Reset system PSoC™ 4 supports several types of resets that guarantee error-free operation during power up and allow the device to reset based on user-supplied external hardware or internal software reset signals. PSoC™ 4 also contains hardware to enable the detection of certain resets.
Page 77: External Reset
PSoC™ 4000T MCU architecture Reset system 14.1.5 External reset External reset (XRES) is a user-supplied reset that causes immediate system reset when asserted. The XRES pin is active low – a high voltage on the pin has no effect and a low voltage causes a reset. The pin is pulled high inside the device.
Page 78: Section D: Digital System
PSoC™ 4000T MCU architecture Digital system Section D: Digital system This section encompasses the following chapters: • “Serial communications block (SCB)” on page 79 • “Timer, counter, and PWM (TCPWM)” on page 140 Top level architecture Digital system block diagram Peripheral Interconnect (MMIO) PCLK High Speed I/O Matrix...
Page 79: Serial Communications Block (Scb)
PSoC™ 4000T MCU architecture Serial communications block (SCB) Serial communications block (SCB) The SCB supports three serial communication protocols: Serial Peripheral Interface (SPI), Universal Asynchronous Receiver Transmitter (UART), and Inter Integrated Circuit (I C or IIC). Only one of the protocols is supported by an SCB at any given time.
Page 80: Clocking Modes
PSoC™ 4000T MCU architecture Serial communications block (SCB) 15.2.1.2 EZ mode In easy (EZ) mode the RAM is used as a single 32-byte buffer. The external master sets a base address and reads and writes start from that base address. EZ Mode is available only for SPI slave and I C slave.
Page 81: Serial Peripheral Interface (Spi)
PSoC™ 4000T MCU architecture Serial communications block (SCB) Table 15-2. Clock configuration and mode support EC_AM_MODE is '0'; 'EC_AM_MODE is '1'; 'EC_AM_MODE is '1'; Mode EC_OP_MODE is ‘0’ EC_OP_MODE is '0’ EC_OP_MODE is '1' FIFO mode EZ mode 15.3 Serial peripheral interface (SPI) The SPI protocol is a synchronous serial interface protocol.
Page 82: General Description
PSoC™ 4000T MCU architecture Serial communications block (SCB) 15.3.2 General description Figure 15-1 illustrates an example of SPI master with four slaves. SCLK MOSI MISO Slave 1 Master Slave Select (SS) 1 Slave 2 Slave Select (SS) 2 Slave 3 Slave Select (SS) 3 Slave 4 Slave Select (SS) 4...
Page 83: Spi Modes Of Operation
PSoC™ 4000T MCU architecture Serial communications block (SCB) 15.3.3 SPI modes of operation 15.3.3.1 Motorola SPI The original SPI protocol was defined by Motorola. It is a full duplex protocol. Multiple data transfers may happen with the SS line held at ‘0’. When not transmitting data, the SS line is held at ‘1’. Clock modes of Motorola SPI The Motorola SPI protocol has four different clock modes based on how data is driven and captured on the MOSI and MISO lines.
Page 84 PSoC™ 4000T MCU architecture Serial communications block (SCB) Figure 15-3 illustrates a single 8-bit data transfer and two successive 8-bit data transfers in mode 0 (CPOL is ‘0’, CPHA is ‘0’). CPOL = 0, CPHA = 0 single data transfer SCLK MOSI MISO...
Page 85 PSoC™ 4000T MCU architecture Serial communications block (SCB) Configuring SCB for SPI Motorola mode To configure the SCB for SPI Motorola mode, set various register bits in the following order: 1. Select SPI by writing ‘01’ to the MODE (bits [25:24]) of the SCB_CTRL register. 2.
Page 86 PSoC™ 4000T MCU architecture Serial communications block (SCB) single data transfer CPOL=0, CPHA=1 SCLK MOSI MISO two successive data transfers CPOL=0, CPHA=1 SCLK LSb MSb MOSI LSb MSb MISO Figure 15-6. SPI TI data transfer example Configuring SCB for SPI TI mode To configure the SCB for SPI TI mode, set various register bits in the following order: 1.
Page 87 PSoC™ 4000T MCU architecture Serial communications block (SCB) 15.3.3.3 National Semiconductors SPI The National Semiconductors’ SPI protocol is a half-duplex protocol. Rather than transmission and reception occurring at the same time, they take turns. The transmission and reception data sizes may differ. A single ‘idle’ bit transfer period separates transfers from reception.
Page 88: Spi Buffer Modes
PSoC™ 4000T MCU architecture Serial communications block (SCB) 15.3.4 SPI buffer modes SPI can operate in two different buffer modes – FIFO and EZ modes. The buffer is used in different ways in each of these modes. The following subsections explain each of these buffer modes in detail. 15.3.5 FIFO mode The FIFO mode has a TX FIFO for the data being transmitted and an RX FIFO for the data received.
Page 89 PSoC™ 4000T MCU architecture Serial communications block (SCB) 15.3.5.1 EZSPI mode The easy SPI (EZSPI) protocol only works in the Motorola mode, with any of the clock modes. It allows communication between master and slave without the need for CPU intervention. The EZSPI protocol defines a single memory buffer with an 5-bit EZ address that indexes the buffer (32-entry array of eight bit per entry) located on the slave device.
Page 90 PSoC™ 4000T MCU architecture Serial communications block (SCB) Command 0x00 : Write EZ address SCLK Command 0x00 EZ Address MOSI MISO EZ address (8 bits) EZ address Command 0x01 : Write DATA SCLK Write DATA Command 0x01 MOSI MISO Write DATA EZ buffer EZ address...
Page 91: Clocking And Oversampling
PSoC™ 4000T MCU architecture Serial communications block (SCB) 1. Select EZ mode by writing ‘1’ to the EZ_MODE bit (bit 10) of the SCB_CTRL register. 2. Set the EC_AM and EC_OP modes in the SCB_CTRL register as appropriate. 3. Set the BYTE_MODE bit of the SCB_CTRL register to ‘1’. 4.
Page 92 PSoC™ 4000T MCU architecture Serial communications block (SCB) • EC_AM_MODE is ‘1’ and EC_OP_MODE is ‘0’: Use this configuration when both Active and Deep Sleep functionality are required. This configuration relies on the externally-clocked functionality to detect the slave selection and relies on the internally-clocked functionality to access the memory buffer. The “hand over”...
Page 93 PSoC™ 4000T MCU architecture Serial communications block (SCB) Table 15-3. SPI modes compatibility Internally clocked (IC) Externally clocked (EC) FIFO FIFO SPI Master SPI Slave a) In SPI slave FIFO mode, the external-clocked logic does selection detection, then triggers an interrupt to wake up the CPU.
Page 94 PSoC™ 4000T MCU architecture Serial communications block (SCB) If after doing these calculations the desired speed cannot be achieved, then consider using the MISO late sample feature of the SCB. This can be done by setting the SPI_CTRL.LATE_MISO_SAMPLE register. MISO late sample tells the SCB to sample the incoming MISO signal on the next edge of SCLK, thus allowing for ½...
Page 95: Enabling And Initializing Spi
PSoC™ 4000T MCU architecture Serial communications block (SCB) 15.3.7 Enabling and initializing SPI The SPI must be programmed in the following order: 1. Program protocol specific information using the SCB_SPI_CTRL register. This includes selecting the sub- modes of the protocol and selecting master-slave functionality. EZSPI can be used with slave mode only. 2.
Page 96: I/O Pad Connection
PSoC™ 4000T MCU architecture Serial communications block (SCB) 15.3.8 I/O pad connection 15.3.8.1 SPI master Figure 15-10 Table 15-4 list the use of the I/O pads for SPI master. spi_clk_out_en spi_clk_out_en spi_ctl spi_clk_out spi_clk_out spi_clk spi_clk_in spi_clk_in Normal output mode spi_select_out_en spi_select_out_en spi_ctl...
Page 97: Spi Slave
PSoC™ 4000T MCU architecture Serial communications block (SCB) 15.3.8.2 SPI slave Figure 15-11 Table 15-5 list the use of I/O pads for SPI Slave. spi_clk_out_en spi_ctl don’t care spi_clk_out spi_clk spi_clk_in spi_clk_in Input only spi_select_out_en spi_ctl don’t care spi_select_out spi_select spi_select_in spi_select_in Input only...
Page 98: Spi Registers
PSoC™ 4000T MCU architecture Serial communications block (SCB) 15.3.8.3 Glitch avoidance at system reset The SPI outputs are in high-impedance digital state when the device is coming out of system reset. This can cause glitches on the outputs. This is important if you are concerned with SPI master SS0 – SS3 or SCLK output pins activity at either device startup or when coming out of Hibernate mode.
Page 99: Uart
PSoC™ 4000T MCU architecture Serial communications block (SCB) 15.4 UART The Universal Asynchronous Receiver/Transmitter (UART) protocol is an asynchronous serial interface protocol. UART communication is typically point-to-point. The UART interface consists of two signals: • TX: Transmitter output • RX: Receiver input Additionally, two side-band signals are used to implement flow control in UART.
Page 100: General Description
PSoC™ 4000T MCU architecture Serial communications block (SCB) 15.4.2 General description Figure 15-12 illustrates a standard UART TX and RX. UART UART Figure 15-12. UART example A typical UART transfer consists of a start bit followed by multiple data bits, optionally followed by a parity bit and finally completed by one or more stop bits.
Page 101 PSoC™ 4000T MCU architecture Serial communications block (SCB) Two successive data transfers (7data bits, 1 parity bit, 2 stop bits) Tx / Rx STOP START DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA START IDLE LEGEND: Tx / Rx : Transmit or Receive line Figure 15-13.
Page 102 PSoC™ 4000T MCU architecture Serial communications block (SCB) Parity This functionality adds a parity bit to the data frame and is used to identify single-bit data frame errors. The parity bit is always directly after the data frame bits. The transmitter calculates the parity bit (when UART_TX_CTRL.PARITY_ENABLED is 1) from the data frame bits, such that data frame bits and parity bit have an even (UART_TX_CTRL.PARITY is 0) or odd (UART_TX_CTRL.PARITY is 1) parity.
Page 103 PSoC™ 4000T MCU architecture Serial communications block (SCB) Figure 15-17 illustrates the process. uart_rx IDLE/STOP START START Active power mode Active A -> DS Deep Sleep DS -> A 2 UART not operational UART RX synchronizes CPU enables Rx functionality UART Rx Setup IOSS/GPIO IOSS/GPIO wake up interrupt...
Page 104 PSoC™ 4000T MCU architecture Serial communications block (SCB) Regular frame uart _ rx STOP START STOP bit 2 bit 3 bit 4 bit 5 bit 6 bit 8 bit 9 Break frame (12 low/0-bit periods) uart _ rx STOP START STOP Figure 15-18.
Page 105 PSoC™ 4000T MCU architecture Serial communications block (SCB) UART MP Master Master Tx Master Rx UART MP UART MP UART MP Slave 1 Slave 2 Slave 3 Figure 15-20. UART MP mode bus connections The main properties of UART_MP mode are: •...
Page 106 PSoC™ 4000T MCU architecture Serial communications block (SCB) 15.4.3.2 UART local interconnect network (LIN) mode The LIN protocol is supported by the SCB as part of the standard UART. LIN is designed with single-master-multi- slave topology. There is one master node and multiple slave nodes on the LIN bus. The SCB UART supports both LIN master and slave functionality.
Page 107 PSoC™ 4000T MCU architecture Serial communications block (SCB) Figure 15-24. LIN frame structure In LIN protocol communication, the least significant bit (LSb) of the data is sent first and the most significant bit (MSb) last. The start bit is encoded as zero and the stop bit is encoded as one. The following sections describe all the byte fields in the LIN frame.
Page 108 PSoC™ 4000T MCU architecture Serial communications block (SCB) Figure 15-27. PID field Data In LIN, every frame can carry a minimum of one byte and maximum of eight bytes of data. Here, the LSb of the data byte is sent first and the MSb of the data byte is sent last. Checksum The checksum is the last byte field in the LIN frame.
Page 109 PSoC™ 4000T MCU architecture Serial communications block (SCB) Before transmitting a master request frame, the master task queries its diagnostic module to see whether it will be transmitted or whether the bus will be silent. A slave response frame header will be sent unconditionally. The slave tasks publish and subscribe to the response according to their diagnostic modules.
Page 110 PSoC™ 4000T MCU architecture Serial communications block (SCB) Two successive data transfers (7 data bits, 1 parity bit, 2 stop bits) without NACK Tx / Rx STOP START DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA START IDLE Two successive data transfers (7data bits, 1 parity bit, 2 stop bits) with NACK Tx / Rx STOP...
Page 111: Clocking And Oversampling
PSoC™ 4000T MCU architecture Serial communications block (SCB) Two successive data transfers (7 data bits, 1 parity bit, 2 stop bits) Tx / Rx STOP START ‘0' START ‘1' ‘0' ‘1' ‘1' ‘0' ‘0' ‘1' ‘1' ‘1' ‘1' IDLE IrDA Tx / Rx LEGEND: Tx / Rx : Transmit or Receive line...
Page 112: Enabling And Initializing The Uart
PSoC™ 4000T MCU architecture Serial communications block (SCB) 15.4.5 Enabling and initializing the UART The UART must be programmed in the following order: 1. Program protocol specific information using the UART_TX_CTRL, UART_RX_CTRL, and UART_FLOW_CTRL registers. This includes selecting the submodes of the protocol, transmitter-receiver functionality, and so on. 2.
Page 113: Smartcard Mode
PSoC™ 4000T MCU architecture Serial communications block (SCB) 15.4.6.2 SmartCard mode Figure 15-31 Table 15-8 list the use of the I/O pads for the SmartCard mode. uart_tx_out_en uart_tx_out_en uart_tx_ctl uart_tx_out Open drain uart_tx_out (pull-up) uart_tx uart_tx_in uart_tx_in uart_rx_out_en uart_rx_ctl uart_rx_out uart_rx_in Figure 15-31.
Page 114: Irda Mode
PSoC™ 4000T MCU architecture Serial communications block (SCB) 15.4.6.4 IrDA mode Figure 15-33 Table 15-10 list the use of the I/O pads for IrDA mode. uart_tx_out_en uart_tx_ctl Normal uart_tx_out uart_tx_out output mode uart_tx IrDA uart_tx_in uart_tx_in transducer module uart_rx_out_en uart_rx_ctl IrDA don t care uart_rx_out...
Page 115: Inter Integrated Circuit (I2C)
PSoC™ 4000T MCU architecture Serial communications block (SCB) 15.5 Inter integrated circuit (I This section explains the I C implementation in the PSoC™ 4 MCU. For more information on the I C protocol specification, refer to the I C-bus specification available on the UM10204. 15.5.1 Features This block supports the following features:...
Page 116: External Electrical Connections
) are primarily determined by the supply voltage, bus speed, and bus capacitance. For detailed information on how to calculate the optimum pull-up resistor value for your design Infineon® recommends using the UM10204 I C-bus specification, available on the UM10204.
Page 117: Terms And Definitions
PSoC™ 4000T MCU architecture Serial communications block (SCB) • = Minimum high-level input noise margin from I C specification • = Total input leakage current of all devices on the bus The supply voltage (V ) limits the minimum pull-up resistor value due to bus devices maximum low output voltage (V ) specifications.
Page 118: Bus Arbitration
PSoC™ 4000T MCU architecture Serial communications block (SCB) 15.5.4.2 Bus arbitration The I C protocol is a multi-master, multi-slave interface. Bus arbitration is implemented on master devices by monitoring the SDA line. Bus collisions are detected when the master observes an SDA line value that is not the same as the value it is driving on the SDA line.
Page 119: Read Transfer
PSoC™ 4000T MCU architecture Serial communications block (SCB) 15.5.5.1 Write transfer • A typical write transfer begins with the master generating a START condition on the I C bus. The master then writes a 7-bit I C slave address and a write indicator (‘0’) after the START condition. The addressed slave transmits an acknowledgment byte by pulling the data line low during the ninth bit time.
Page 120: I2C Buffer Modes
PSoC™ 4000T MCU architecture Serial communications block (SCB) • A typical read transfer begins with the master generating a START condition on the I C bus. The master then writes a 7-bit I C slave address and a read indicator (‘1’) after the START condition. The addressed slave transmits an acknowledgment by pulling the data line low during the ninth bit time.
Page 121 15.5.6.2 EZI2C mode The Easy I C (EZI2C) protocol is a unique communication scheme built on top of the I C protocol by Infineon®. It uses a meta protocol around the standard I C protocol to communicate to an I C slave using indexed memory transfers.
Page 122 PSoC™ 4000T MCU architecture Serial communications block (SCB) Write data transfer (single write data) START Slave address (7 bits) Write ACK EZ address (8 bits) Write Data (8 bits) STOP EZ address Data EZ Buffer (32 bytes SRAM) Address Read data transfer (single read data) START Slave address (7 bits) Read...
Page 123: Clocking And Oversampling
PSoC™ 4000T MCU architecture Serial communications block (SCB) Note: • The interrupt bit WAKE_UP (bit 0) of the SCB_INTR_I2C_EC register must be enabled for the I C to wake up the device on slave address match while switching to the Sleep mode •...
Page 124 PSoC™ 4000T MCU architecture Serial communications block (SCB) the maximum blocking period of one serial interface bit period measures 10 µs (approximately 208 clock cycles on a 48 MHz SCB input clock). This option provides normal SCB register functionality, but the blocking time introduces additional internal bus wait states.
Page 125 PSoC™ 4000T MCU architecture Serial communications block (SCB) Table 15-16 lists the useful combinations of glitch filters. Table 15-16. Glitch filter combinations AF_in AF_out DF_in Comments Used when operating in internally-clocked mode and in master in fast-mode plus (1-MHz speed mode) Used when operating in internally-clocked mode (EC_OP_MODE is '0') Used when operating in externally-clocked mode (EC_OP_MODE is '1').
Page 126 PSoC™ 4000T MCU architecture Serial communications block (SCB) C master clock synchronization The HIGH_PHASE_OVS counter does not start counting until the SCB detects that the SCL line is high. This is not the same as when the SCB sets the SCL high. The differences are explained by three delays: 1.
Page 127: Enabling And Initializing The I2C
PSoC™ 4000T MCU architecture Serial communications block (SCB) The result that yields the largest period from the two sets of equations above should be used to set the minimum period of clk_scb. Master-Slave To configure the I C for master-slave mode, write ‘1’ to the MASTER_MODE(bit-31) and SLAVE_MODE(bit-30) of the I2C_CTRL register.
Page 128: I/O Pad Connections
PSoC™ 4000T MCU architecture Serial communications block (SCB) 15.5.9 I/O pad connections i2c_ic_block_ec i2c_ctl i2c_ic_scl_out Open drain i2c_ic_sda_out (pull-up) i2c_scl i2c_scl_in i2c_scl_in Filter i2c_sda_in Filter i2c_ec_ctl i2c_ec_scl_out i2c_ec_sda_out i2c_sda i2c_sda_in Filter i2c_scl_in Open drain i2c_sda_in (pull-up) Figure 15-41. I C I/O pad connections Table 15-19.
Page 129: I2C Registers
PSoC™ 4000T MCU architecture Serial communications block (SCB) 15.6 C registers The I C interface is controlled by reading and writing a set of configuration, control, and status registers, as listed Table 15-20. Table 15-20. I C registers Register Function Enables the SCB block and selects the type of serial interface (SPI, UART, I SCB_CTRL Also used to select internally and externally clocked operation and EZ and...
Page 130: Scb Interrupts
PSoC™ 4000T MCU architecture Serial communications block (SCB) Table 15-20. I C registers (continued) Register Function Holds the data read from the receiver FIFO. Reading a data frame does not SCB_RX_FIFO_RD_SILENT remove the data frame from the FIFO; behavior is similar to that of a PEEK operation.
Page 131 PSoC™ 4000T MCU architecture Serial communications block (SCB) • INTR_M_MASK: The bit in this register masks the interrupt sources. Only the interrupt sources with their masks enabled can trigger the interrupt. • INTR_M_MASKED: This register provides the instantaneous value of the interrupts after they are masked. It provides logical and corresponding request and mask bits.
Page 132: Spi Interrupts
PSoC™ 4000T MCU architecture Serial communications block (SCB) 15.7.1 SPI interrupts The SPI interrupts can be classified as master interrupts, slave interrupts, TX interrupts, RX interrupts, and externally clocked (EC) mode interrupts. Each interrupt output is the logical OR of the group of all possible interrupt sources classified under the section.
Page 133 PSoC™ 4000T MCU architecture Serial communications block (SCB) Figure 15-43 Figure 15-44 show how each of the interrupts are triggered. Figure 15-43 shows the TX buffer and the corresponding interrupts while Figure 15-44 shows all the corresponding interrupts for the RX buffer. The FIFO has 32 bytes split into 16 bytes for TX and 16 bytes for RX instead of the 8 bytes shown below.
Page 134 PSoC™ 4000T MCU architecture Serial communications block (SCB) Component Started Recevice 1 byte Receive 4 more byte Receive 3 more bytes Receive 3 more bytes RX FIFO Not Empty = 1 RX FIFO Not Empty = 0 RX FIFO Not Empty = 1 RX FIFO Not Empty = 1 RX FIFO Not Empty = 1 RX FIFO Level...
Page 135: Uart Interrupts
PSoC™ 4000T MCU architecture Serial communications block (SCB) 15.7.2 UART interrupts The UART interrupts can be classified as TX interrupts and RX interrupts. Each interrupt output is the logical OR of the group of all possible interrupt sources classified under the section. For example, the TX interrupt output is the logical OR of the group of all possible TX interrupt sources.
Page 136 PSoC™ 4000T MCU architecture Serial communications block (SCB) – LIN break detection is successful – The line is ‘0’ for UART_RX_CTRL.BREAK_WIDTH + 1 bit period. Can occur at any time to address unanticipated break fields; that is, “break-in-data” is supported. This feature is supported for the UART standard and LIN submodes.
Page 137 PSoC™ 4000T MCU architecture Serial communications block (SCB) Component Started Recevice 1 byte Receive 4 more byte Receive 3 more bytes Receive 3 more bytes RX FIFO Not Empty = 1 RX FIFO Not Empty = 0 RX FIFO Not Empty = 1 RX FIFO Not Empty = 1 RX FIFO Not Empty = 1 RX FIFO Level...
Page 138: I2C Interrupts
PSoC™ 4000T MCU architecture Serial communications block (SCB) 15.7.3 C interrupts C interrupts can be classified as master interrupts, slave interrupts, TX interrupts, RX interrupts, and externally clocked (EC) mode interrupts. Each interrupt output is the logical OR of the group of all possible interrupt sources classified under the section.
Page 139 PSoC™ 4000T MCU architecture Serial communications block (SCB) • C TX – TX trigger – TX FIFO has fewer entries than the value specified by TRIGGER_LEVEL in SCB_TX_FIFO_CTRL. – TX FIFO not full – At least one data element can be written into the TX FIFO. –...
Page 140: Timer, Counter, And Pwm (Tcpwm)
PSoC™ 4000T MCU architecture Timer, counter, and PWM (TCPWM) Timer, counter, and PWM (TCPWM) The Timer, Counter, Pulse Width Modulator (TCPWM) block in the PSoC™ 4 MCU uses a 16-bit counter, which can be configured as a timer, counter, pulse width modulator (PWM), or quadrature decoder. The block can be used to measure the period and pulse width of an input signal (times), find the number of times a particular event occurs (counter), generate PWM signals, or decode quadrature signals.
Page 141: Enabling And Disabling Counters In A Tcpwm Block
PSoC™ 4000T MCU architecture Timer, counter, and PWM (TCPWM) The TCPWM block can contain up to two counters. Each counter can be 16-bit wide. The three main registers that control the counters are: • TCPWM_CNT_CC is used to capture the counter value in CAPTURE mode. In all other modes this value is compared to the counter value.
Page 142: Trigger Inputs
PSoC™ 4000T MCU architecture Timer, counter, and PWM (TCPWM) 16.2.2.2 Count input The counter increments or decrements on a prescaled clock in which the count input is active – “active count”. When the count input is configured as level, the count value is changed on each prescaled clk_counter edge in which the count input is high.
Page 143 PSoC™ 4000T MCU architecture Timer, counter, and PWM (TCPWM) Before going to the counter each Trigger_IN can pass through a positive edge detector, negative edge detector, both edge detector, or pass straight through to the counter. This is controlled using TCPWM_CNT_TR_CTRL1. In the quadrature mode, edge detection is done using clk_counter.
Page 144 PSoC™ 4000T MCU architecture Timer, counter, and PWM (TCPWM) Trigger input sources Rising edge detect Falling edge detect Rising or Falling event edge detect Trigger_In[14] No edge detect TCPWM_CMD registers (software generated) TCPWM_CNT_TR_CTRL0 TCPWM_CNT_TR_CTRL1 Figure 16-5. TCPWM input events To use GPIOs for trigger, HSIOM_PORT_SELx register should TCPWM_CNT0_TR_CTRL0 be written...
Page 145: Trigger Outputs
PSoC™ 4000T MCU architecture Timer, counter, and PWM (TCPWM) Note: • All trigger inputs are synchronized to “clk_hf”. • When more than one event occurs in the same clk_counter period, one or more events may be missed. This can happen for high-frequency events (frequencies close to the counter frequency) and a timer configuration in which a pre-scaled (divided) clk_counter is used.
Page 146: Pwm Outputs
PSoC™ 4000T MCU architecture Timer, counter, and PWM (TCPWM) 16.2.6 PWM outputs Each counter has two outputs, pwm (line_out) and pwm_n (line_compl_out) (complementary of pwm). Note that the OV, UN, and CC conditions are used to drive line_out and line_compl_out, by configuring the TCPWM_CNT_TR_CTRL2 register (see Table 16-2).
Page 147: Operation Modes
PSoC™ 4000T MCU architecture Timer, counter, and PWM (TCPWM) 16.3 Operation modes The counter block can function in six operational modes, as shown in Table 16-4. The MODE [26:24] field of the counter control register (TCPWM_CNTx_CTRL) configures the counter in the specific operational mode. Table 16-4.
Page 148: Timer Mode
PSoC™ 4000T MCU architecture Timer, counter, and PWM (TCPWM) 16.3.1 Timer mode The timer mode can be used to measure how long an event takes or the time difference between two events. The timer functionality increments/decrements a counter between 0 and the value stored in the PERIOD register. When the counter is running, the count value stored in the COUNTER register is compared with the compare/capture register (CC).
Page 149 PSoC™ 4000T MCU architecture Timer, counter, and PWM (TCPWM) Table 16-8 lists the trigger outputs and the conditions when they are triggered. Table 16-8. Timer mode trigger outputs Trigger outputs Description cc_match (CC) Counter changes from a state in which COUNTER equals CC. Underflow (UN) Counter is decrementing and changes from a state in which COUNTER equals ‘0’.
Page 150 PSoC™ 4000T MCU architecture Timer, counter, and PWM (TCPWM) Figure 16-8 illustrates a timer in up-counting mode. The counter is initialized (to 0) and started with a software- based reload event. Note: • PERIOD is 4, resulting in an effective repeating counter pattern of 4+1 = 5 clk_counter periods. The CC register is 2, and sets the condition for a cc_match event.
Page 151 PSoC™ 4000T MCU architecture Timer, counter, and PWM (TCPWM) Figure 16-10 illustrates clock pre-scaling. Note that the counter is only incremented every other counter cycle. MODE = TIMER UP_DOWN_MODE = COUNT_UP ONE_SHOT = 1 PRESCALE = DIV_BY_2 reload PERIOD = 4 CC = 2 Underflow (UN) Overflow (OV)
Page 152 PSoC™ 4000T MCU architecture Timer, counter, and PWM (TCPWM) Figure 16-13 illustrates a timer in down counting mode. The counter is initialized (to PERIOD) and started with a software-based reload event. Note: • When the counter changes from a state in which COUNTER is 0, a UN and TC events are generated. •...
Page 153 PSoC™ 4000T MCU architecture Timer, counter, and PWM (TCPWM) Figure 16-15 illustrates a timer in up/down counting mode 1, with different CC values. Note: • When CC is 0, the cc_match event is generated at the start of the period (when the counter changes from a state in which COUNTER is 0).
Page 154: Capture Mode
PSoC™ 4000T MCU architecture Timer, counter, and PWM (TCPWM) 16.3.1.1 Configuring counter for timer mode The steps to configure the counter for Timer mode of operation and the affected register bits are as follows. 1. Disable the counter by writing ‘0’ to the COUNTER_ENABLED field of the TCPWM_CTRL register. 2.
Page 155 PSoC™ 4000T MCU architecture Timer, counter, and PWM (TCPWM) Table 16-12. Capture mode supported features Supported features Description Clock pre-scaling Pre-scales the counter clock clk_counter. Counter is stopped by hardware, after a single period of the counter: One-shot • COUNT_UP: on an overflow event. •...
Page 156 PSoC™ 4000T MCU architecture Timer, counter, and PWM (TCPWM) Capture Interrupt interrupt Reload generation Start PERIOD cc_match tr_cc_match Stop Trigger Count underflow tr_underflow generation overflow tr_overflow Capture COUNTER clk_counter CC_BUFF Figure 16-17. Capture functionality Figure 16-18 illustrates capture behavior in the up counting mode. Note: •...
Page 157: Quadrature Decoder Mode
PSoC™ 4000T MCU architecture Timer, counter, and PWM (TCPWM) MODE = CAPTURE UP_DOWN_MODE = COUNT_UP CAPTURE_EDGE = RISING_EDGE missed capture event reload capture CC_BUFF PERIOD = 4 Underflow (UN) Overflow (OV) Terminal Count (TC) Compare/Capture (CC) Figure 16-19. Multiple events detected before active-count 16.3.2.1 Configuring counter for capture mode The steps to configure the counter for Capture mode operation and the affected register bits are as follows.
Page 158 PSoC™ 4000T MCU architecture Timer, counter, and PWM (TCPWM) Table 16-16. Quadrature mode trigger input description Trigger input Usage This event acts as a quadrature index input. It initializes the counter to the counter reload/index midpoint 0x8000 and starts the quadrature functionality. Rising edge event detection or falling edge detection mode must be used.
Page 159 PSoC™ 4000T MCU architecture Timer, counter, and PWM (TCPWM) Quadrature Interrupt interrupt 0x0000 Generation Reload/Index 0x8000 (+/- 1) Start/phiB Trigger Stop cc_match tr_cc_match Generation Count/phiA COUNTER 0xFFFF clk_counter CC_BUFF Figure 16-20. Quadrature functionality (16-bit example) Quadrature functionality is described as follows: •...
Page 160 PSoC™ 4000T MCU architecture Timer, counter, and PWM (TCPWM) phiA phiB Quadrature decoding QUADRATURE_MODE = X1 incr1 decr1 Quadrature decoding QUADRATURE_MODE = X2 Two times the events of X1 mode incr1 decr1 Quadrature decoding QUADRATURE_MODE = X4 Four times the events of X1 mode incr1 decr1 Figure 16-21.
Page 161 PSoC™ 4000T MCU architecture Timer, counter, and PWM (TCPWM) Figure 16-23 illustrate quadrature functionality for different event scenarios (including scenarios with coinciding events). In all scenarios, the first reload/index event is generated by software when the counter is not yet running. Quadrature decoding “counter cycle”...
Page 162: Pulse Width Modulation Mode
PSoC™ 4000T MCU architecture Timer, counter, and PWM (TCPWM) 16.3.3.1 Configuring counter for quadrature mode The steps to configure the counter for quadrature mode of operation and the affected register bits are as follows. 1. Disable the counter by writing ‘0’ to the COUNTER_ENABLED field of the TCPWM_CTRL register. 2.
Page 163: Supported Features
PSoC™ 4000T MCU architecture Timer, counter, and PWM (TCPWM) Table 16-21. PWM mode trigger input description Trigger inputs Usage count Count event increments/decrements the counter. This event acts as a swap event. When this event is active, the CC/CC_BUFF and PERIOD/PERIOD_BUFF registers are exchanged on a tc event (when specified by CTRL.AUTO_RELOAD_CC and CTRL.AUTO_RELOAD_PERIOD).
Page 164: Trigger Output
PSoC™ 4000T MCU architecture Timer, counter, and PWM (TCPWM) Table 16-22. PWM mode supported features Supported features Description Specified by UP_DOWN_MODE: • COUNT_UP: The counter counts from 0 to PERIOD. Generates a left-aligned PWM output. Alignment (Up/down • COUNT_DOWN: The counter counts from PERIOD to 0. Generates a right-aligned modes) PWM output.
Page 165 PSoC™ 4000T MCU architecture Timer, counter, and PWM (TCPWM) Table 16-25. PWM mode PWM outputs PWM outputs Description line_out PWM output. line_compl_out Complementary PWM output. Note that the cc_match event generation in COUNT_UP and COUNT_DOWN modes are different from the generation in other functional modes or counting modes.
Page 166 PSoC™ 4000T MCU architecture Timer, counter, and PWM (TCPWM) Note: • When the counter changes from a state in which COUNTER is 4, an overflow and tc event are generated. • When the counter changes to a state in which COUNTER is 2, a cc_match event is generated. •...
Page 167 PSoC™ 4000T MCU architecture Timer, counter, and PWM (TCPWM) Figure 16-28 illustrates a PWM in down counting mode. The counter is initialized (to PERIOD) and started with a software-based reload event. Note: • When the counter changes from a state in which COUNTER is 0, an underflow and tc event are generated. •...
Page 168 PSoC™ 4000T MCU architecture Timer, counter, and PWM (TCPWM) Figure 16-30 illustrates a PWM in up/down counting mode. The counter is initialized (to 1) and started with a software-based reload event. Note: • When the counter changes from a state in which COUNTER is 4, an overflow is generated. •...
Page 169 PSoC™ 4000T MCU architecture Timer, counter, and PWM (TCPWM) Different stop/kill modes exist. The mode is specified by PWM_STOP_ON_KILL and PWM_SYNC_KILL. The following three modes are supported: • PWM_STOP_ON_KILL is ‘1’ (PWM_SYNC_KILL is don’t care): Stop on Kill mode. This mode stops the counter on a stop/kill event.
Page 170 PSoC™ 4000T MCU architecture Timer, counter, and PWM (TCPWM) Right aligned PWM PWM_STOP_ON_KILL = 0, PWM_SYNC_KILL = 1 “line_out” and “line_compl_out” set to STOP_EDGE = RISING_EDGE counter does NOT stop programmed polarity “dead time” = 0 “line_out polarity” = 0, “line_compl_out polarity” = 0 cc_match line kill...
Page 171 PSoC™ 4000T MCU architecture Timer, counter, and PWM (TCPWM) The previous section addressed synchronized updates of the CC/CC_BUFF and PERIOD/PERIOD_BUFF registers of a single PWM using a software-generated swap event. During motor control, three PWMs work in unison and updates to all period and compare register pairs should be synchronized. All three PWMs have synchronized periods and as a result have synchronized tc events.
Page 172 PSoC™ 4000T MCU architecture Timer, counter, and PWM (TCPWM) Figure 16-37 illustrates how the COUNT_UPDN2 mode is used to generate an asymmetric PWM. MODE = PWM UP_DOWN_MODE = COUNT_UPDN2 CC_BUFF reload PERIOD = 4 Underflow (UN) Overflow (OV) Terminal Count (TC) Compare/Capture (CC) Asymmetric PWM CC = PERIOD –...
Page 173: Pulse Width Modulation With Dead Time Mode
PSoC™ 4000T MCU architecture Timer, counter, and PWM (TCPWM) 16.3.4.2 Configuring counter for PWM mode The steps to configure the counter for the PWM mode of operation and the affected register bits are as follows. 1. Disable the counter by writing ‘0’ to the COUNTER_ENABLED field of the TCPWM_CTRL register. 2.
Page 174 PSoC™ 4000T MCU architecture Timer, counter, and PWM (TCPWM) Dead time insertion is a step that operates on a preliminary PWM output signal line, as illustrated in Figure 16-39. Figure 16-40 illustrates dead time insertion for different dead times and different output signal polarity settings. input MODE = PWM_DT “dead time”...
Page 175: Pulse Width Modulation Pseudo-Random Mode (Pwm_Pr)
PSoC™ 4000T MCU architecture Timer, counter, and PWM (TCPWM) 16.3.5.1 Configuring counter for PWM with dead time mode The steps to configure the counter for PWM with Dead Time mode of operation and the affected register bits are as follows: 1.
Page 176 PSoC™ 4000T MCU architecture Timer, counter, and PWM (TCPWM) Note: Event detection is on the “clk_counter” while in Quadrature mode and “clk_hf_counter” for all other modes. Table 16-27. PWM_PR supported features Supported features Description Clock pre-scaling Pre-scales the counter clock, clk_counter. Counter is stopped by hardware, after a single period of the counter (counter value One-shot equals period value PERIOD).
Page 177 PSoC™ 4000T MCU architecture Timer, counter, and PWM (TCPWM) The PWM_PR functionality is described as follows: • The counter value COUNTER is initialized by software (to a value different from 0). • A reload or start event starts PWM_PR operation. •...
Page 178 PSoC™ 4000T MCU architecture Timer, counter, and PWM (TCPWM) MODE = PWM_PR COUNTER is exactly 0xe771 reload 0xFFFF PERIOD = 0xe771 CC = 0x4000 cc_match line Only the lower 15 bits of the counter value are used. Figure 16-43. PWM_PR output 16.3.6.1 Configuring counter for pseudo-random PWM mode The steps to configure the counter for pseudo-random PWM mode of operation and the affected register bits are as follows:...
Page 179: Tcpwm Registers
PSoC™ 4000T MCU architecture Timer, counter, and PWM (TCPWM) 16.4 TCPWM registers Table 16-31. List of TCPWM registers Register Comment Features TCPWM_CTRL TCPWM Control Register Enables the counter block TCPWM_CMD TCPWM Command Register Generates software events TCPWM Counter Interrupt Cause Determines the source of the combined TCPWM_INTR_CAUSE Register...
Page 180: Section E: Analog System
PSoC™ 4000T MCU architecture Analog system Section E: Analog system This section encompasses the following chapter: • “CAPSENSE™” on page 181 Top level architecture Analog system block diagram Peripherals Peripheral Interconnect ( MMIO) PCLK High Speed I/O Matrix Power Modes Active / Sleep 21x GPIOs (fine pitch) DeepSleep...
Page 181: Capsense
PSoC™ 4000T MCU architecture CAPSENSE™ CAPSENSE™ CAPSENSE™ is supported in PSoC™ 4000T via the MSCLP CAPSENSE™ block. There is one MSCLP block in the PSoC™ 4000T which can be used to scan sense inputs autonomously (without CPU sequencing and intervention) in Deep Sleep and active modes.
Page 182: Section F: Program And Debug
PSoC™ 4000T MCU architecture Program and debug Section F: Program and debug This section encompasses the following chapters: • “Program and debug interface” on page 183 • “Nonvolatile memory programming” on page 192 Top level architecture Program and debug block diagram CPU Subsystem SWD/TC SPCIF...
Page 183: Program And Debug Interface
The PSoC™ 4 Program and Debug interface provides a communication gateway for an external device to perform programming or debugging. The external device can be a Infineon®-supplied programmer and debugger, or a third-party device that supports programming and debugging. The serial wire debug (SWD) interface is used as the communication protocol between the external device and PSoC™...
Page 184: Serial Wire Debug (Swd) Interface
PSoC™ 4000T MCU architecture Program and debug interface 18.3 Serial wire debug (SWD) interface PSoC™ 4’s Cortex®-M0+ supports programming and debugging through the SWD interface. The SWD protocol is a packet-based serial transaction protocol. At the pin level, it uses a single bidirectional data signal (SWDIO) and a unidirectional clock signal (SWDCK).
Page 185: Swd Timing Details
PSoC™ 4000T MCU architecture Program and debug interface 2. Target Acknowledge Response Phase: SWDIO driven by the target Note: The ACK[2:0] bits represent the target to host response, indicating failure or success, among other results. See Table 18-3 for definitions. ACK bits are transmitted with the LSB first. 3.
Page 186: Ack Details
PSoC™ 4000T MCU architecture Program and debug interface 18.3.2 ACK details The acknowledge (ACK) bit-field is used to communicate the status of the previous transfer. OK ACK means that previous packet was successful. A WAIT response requires a data phase. For a FAULT status, the programming operation should be aborted immediately.
Page 187: Debug Port (Dp) Registers
PSoC™ 4000T MCU architecture Program and debug interface 18.4.1 Debug port (DP) registers Table 18-3 shows the Cortex®-M0+ DP registers used for programming and debugging, along with the corresponding SWD address bit selections. The APnDP bit is always zero for DP register accesses. Two address bits (A[3:2]) are used for selecting among the different DP registers.
Page 188: Programming The Psoc™ 4 Device
PSoC™ 4000T MCU architecture Program and debug interface 18.5 Programming the PSoC™ 4 device PSoC™ 4 is programmed using the following sequence. Refer to see the CY8C4xxx, CYBLxxxx programming specifications for complete details on the programming algorithm, timing specifications, and hardware configuration required for programming.
Page 189: Swd Programming Mode Entry
PSoC™ 4000T MCU architecture Program and debug interface 18.5.2 SWD programming mode entry After the SWD port is acquired, the host must enter the device programming mode within a specific time window. This is done by setting the TEST_MODE bit (bit 31) in the test mode control register (MODE register). The debug port should also be configured before entering the device programming mode.
Page 190: Breakpoint Unit (Bpu)
PSoC™ 4000T MCU architecture Program and debug interface 18.6.2 Breakpoint unit (BPU) The BPU provides breakpoint functionality on instruction fetches. The Cortex®-M0+ DAP in PSoC™ 4 supports up to four hardware breakpoints. Along with the hardware breakpoints, any number of software breakpoints can be created by using the BKPT instruction in the Cortex®-M0+.
Page 191: Registers
PSoC™ 4000T MCU architecture Program and debug interface 18.7 Registers Table 18-5. List of registers Register name Description CM0P_DHCSR Debug Halting Control and Status Register CM0P_DFSR Debug Fault Status Register CM0P_DCRSR Debug Core Register Selector Register CM0P_DCRDR Debug Core Register Data Register CM0P_DEMCR Debug Exception and Monitor Control Register CM0P_BP_CTRL...
Page 192: Nonvolatile Memory Programming
Infineon®-supplied programmers and other third-party programmers can use these functions to program the PSoC™ 4 device with the data in an application hex file. They can also be used to perform bootload operations where the CPU will update a portion of the flash memory.
Page 193: System Call Implementation
PSoC™ 4000T MCU architecture Nonvolatile memory programming 19.3 System call implementation A system call consists of the following items: • Opcode: A unique 8-bit opcode • Parameters: Two 8-bit parameters are mandatory for all system calls. These parameters are referred to as key1 and key2, and are defined as follows: key1 = 0xB6 key2 = 0xD3 + Opcode...
Page 194: Performing A System Call
PSoC™ 4000T MCU architecture Nonvolatile memory programming 19.4.1 Performing a system call The steps to initiate a system call are as follows: 1. Set up the function parameters: The two possible methods for preparing the function parameters (key1, key2, additional parameters) are: a) Write the function parameters to the CPUSS_SYSARG register: This method is used for functions that retrieve their parameters from the CPUSS_SYSARG register.
Page 195: System Calls
PSoC™ 4000T MCU architecture Nonvolatile memory programming 19.5 System calls Table 19-1 lists all the system calls supported in PSoC™ 4 along with the function description and availability in device protection modes. See the “Device security” on page 41 for more information on the device protection settings.
Page 196: Silicon Id
PSoC™ 4000T MCU architecture Nonvolatile memory programming 19.5.1 Silicon ID This function returns a 12-bit family ID, 16-bit silicon ID, and an 8-bit revision ID, and the current device protection mode. These values are returned to the CPUSS_SYSARG and CPUSS_SYSREQ registers. Parameters are passed through the CPUSS_SYSARG and CPUSS_SYSREQ registers.
Page 197: Load Flash Bytes
PSoC™ 4000T MCU architecture Nonvolatile memory programming 19.5.3 Load flash bytes This function loads the page latch buffer with data to be programmed into a row of flash. The load size can range from 1-byte to the maximum number of bytes in a flash row, which is 128 bytes. Data is loaded into the page latch buffer starting at the location specified by the “Byte Addr”...
Page 198: Write Row
PSoC™ 4000T MCU architecture Nonvolatile memory programming Return Address Return Value Description CPUSS_SYSARG register Bits [31:28] Success status code Bits [27:0] 0xXXXXXXX Not used (don’t care) 19.5.4 Write row This function erases and then programs the addressed row of flash with the data in the page latch buffer. If all data in the page latch buffer is 0, then the program is skipped.
Page 199: Program Row
PSoC™ 4000T MCU architecture Nonvolatile memory programming 19.5.5 Program row This function programs the addressed row of the flash with data in the page latch buffer. If all data in the page latch buffer is 0, then the program is skipped. The row must be in an erased state before calling this function. It clears the page latch buffer contents after the row is programmed.
Page 200: Erase All
PSoC™ 4000T MCU architecture Nonvolatile memory programming 19.5.6 Erase all This function erases all the user code in the flash main arrays and the row-level protection data in supervisory flash row 0 of each flash macro. Usage Requirements: Call the Configure Clock API before calling this function. The Configure Clock API ensures that the charge pump clock (clk_pump) and the HFCLK (clk_hf) are set to IMO at 48 MHz.
Page 201: Checksum
PSoC™ 4000T MCU architecture Nonvolatile memory programming 19.5.7 Checksum This function reads either the whole flash memory or a row of flash and returns the 24-bit sum of each byte read in that flash region. When performing a checksum on the whole flash, the user code and supervisory flash regions are included.
Page 202: Write Protection
PSoC™ 4000T MCU architecture Nonvolatile memory programming 19.5.8 Write protection This function programs both the flash row-level protection settings and the device protection settings in the supervisory flash row. The flash row-level protection settings are programmed separately for each flash macro in the device.
Page 203: Non-Blocking Write Row
PSoC™ 4000T MCU architecture Nonvolatile memory programming 19.5.9 Non-blocking write row This function is used when a flash row needs to be written by the CM0+ CPU in a non-blocking manner, so that the CPU can execute code from SRAM while the write operation is being done. The explanation of non-blocking system calls is explained in “Blocking and non-blocking system calls”...
Page 204: Non-Blocking Program Row
PSoC™ 4000T MCU architecture Nonvolatile memory programming 19.5.10 Non-blocking program row This function is used when a flash row needs to be programmed by the CM0+ CPU in a non-blocking manner, so that the CPU can execute code from the SRAM when the program operation is being done. The explanation of non-blocking system calls is explained in “Blocking and non-blocking system calls”...
Page 205: Resume Non-Blocking
PSoC™ 4000T MCU architecture Nonvolatile memory programming 19.5.11 Resume non-blocking This function completes the additional phases of erase and program that were started using the non-blocking write row and non-blocking program row system calls. This function must be called thrice following a call to Non- Blocking Write Row or once following a call to Non-Blocking Program Row from the SPC ISR.
Page 206: System Call Status
PSoC™ 4000T MCU architecture Nonvolatile memory programming 19.6 System call status At the end of every system call, a status code is written over the arguments in the CPUSS_SYSARG register. A success status is 0xAXXXXXXX, where X indicates don’t care values or return data in the case of the system calls that return a value.
Page 207: Non-Blocking System Call Pseudo Code
PSoC™ 4000T MCU architecture Nonvolatile memory programming 19.7 Non-blocking system call pseudo code This section contains pseudo code to demonstrate how to set up a non-blocking system call and execute code out of SRAM during the flash programming operations. #define REG(addr)(*((volatile uint32 *) (addr))) #define CM0_ISER_REG REG( 0xE000E100 ) #define CPUSS_CONFIG_REGREG( 0x40100000 ) #define CPUSS_SYSREQ_REG REG( 0x40100004 )
Page 208 PSoC™ 4000T MCU architecture Nonvolatile memory programming * Write key1, key2, byte address, and macro sel parameters to SRAM REG( 0x20000000 ) = 0x0000D7B6; //Write load size param (128 bytes) to SRAM REG( 0x20000004 ) = 0x0000007F; for(i = 0; i < ROW_SIZE/4; i += 1) REG( 0x20000008 + i*4 ) = 0xDADADADA;...
Page 209: Revision History
PSoC™ 4000T MCU architecture Revision history Revision history Document Date of release Description of changes version 2022-01-19 Initial version of PSoC™ 4000T MCU architecture TRM. Chapter 1. Introduction: Updated section 1.2 Features. Updated section 1.5.1 CAPSENSE™. Chapter 5 Interrupts Updated Table 5-2: Updated MSCv3 to MSC and MSCv3LP to MSCLP. Chapter 7 I/O system Updated section 7.6: Added a paragraph on Port Interrupt Cause Register.
Page 210 All referenced product or service names and trademarks are the property of their respective owners. The Bluetooth® word mark and logos are registered trademarks owned by Bluetooth SIG, Inc., and any use of such marks by Infineon is under license.

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