Infineon AURIX TC33xEXT Manual
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Infineon AURIX TC33xEXT Manual

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A U R I X ™ T C 3 3 x E X T
About this document
Scope and purpose
The Appendix supplies information specific for the TC33xEXT supplementing the family documentation.
User's Manual
Please read the Important Notice and Warnings at the end of this document
www.infineon.com
OPEN MARKET VERSION
V2.0.0
2021-02

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Summary of Contents for Infineon AURIX TC33xEXT

  • Page 1 A U R I X ™ T C 3 3 x E X T About this document Scope and purpose The Appendix supplies information specific for the TC33xEXT supplementing the family documentation. User’s Manual Please read the Important Notice and Warnings at the end of this document V2.0.0 www.infineon.com 2021-02 OPEN MARKET VERSION...

  • Page 2: Table Of Contents

    AURIX™ TC33xEXT Table of Contents About this document............Preface-1 Table of Contents .
  • Page 3 AURIX™ TC33xEXT Data Memory Unit (DMU) ..............6-5 6.3.1 TC33xEXT Specific Register Set .
  • Page 4 AURIX™ TC33xEXT 14.3 Pn Registers ................14-23 14.3.1 SPB bus slave interface .
  • Page 5 AURIX™ TC33xEXT 21.5 Revision History ................21-4 Radar Interface (RIF) .
  • Page 6 AURIX™ TC33xEXT 30.4 Revision History ................30-8 Enhanced Delta-Sigma Analog-to-Digital Converter (EDSADC) .
  • Page 7 AURIX™ TC33xEXT 42.9 Interrupt Service Requests ............. . . 42-20 42.10 Clocks .

  • Page 8: Introduction

    AURIX™ TC33xEXT Introduction Introduction For Introduction, block diagrams and feature set consult the family document. For Pinning consult the Data Sheet. User’s Manual V2.0.0 2021-02 OPEN MARKET VERSION...

  • Page 9: Memory Maps (Memmap)

    AURIX™ TC33xEXT Memory Maps (MEMMAP) Memory Maps (MEMMAP) This is the automatically generated memory map of the TC33xEXT. Overview The memory map describes the address locations and access possibilities for the units, memories, and reserved areas as “seen” from the different on-chip buses’ point of view. Functional Description The bus-specific address maps describe how the different bus master devices react on accesses to on-chip memories and modules, and which address ranges are valid or invalid for the corresponding buses.

  • Page 10: Bus Fabric Sri

    AURIX™ TC33xEXT Memory Maps (MEMMAP) The attribute of these segments (cached / non-cached) can be partially configured for each CPUs data and program side individually (see CPU chapter: Physical Memory Attribute Registers, PMAx). Segment 8 This memory segment allows cached access to PFlash and BROM. Segment 9 This memory segment allows cached access to LMU and to EMEM.
  • Page 11 AURIX™ TC33xEXT Memory Maps (MEMMAP) Table 2 Address Map as seen by Bus Masters on Bus SRI (cont’d) Address Range Size Unit Access Type from Read Write 601C0000 601C2FFF 12 Kbyte Program Cache TAG RAM (CPU1) 601C3000 6FFFFFFF Reserved 70000000 7002FFFF 192 Kbyte Data ScratchPad RAM (CPU0)
  • Page 12 AURIX™ TC33xEXT Memory Maps (MEMMAP) Table 2 Address Map as seen by Bus Masters on Bus SRI (cont’d) Address Range Size Unit Access Type from Read Write AF400000 AF405FFF 24 Kbyte UCB_BMHD0_ORIG (UCB) UCB_BMHD1_ORIG (UCB) UCB_BMHD2_ORIG (UCB) UCB_BMHD3_ORIG (UCB) UCB_SSW (UCB) UCB_USER (UCB) UCB_TEST (UCB) UCB_HSMCFG (UCB)
  • Page 13 AURIX™ TC33xEXT Memory Maps (MEMMAP) Table 2 Address Map as seen by Bus Masters on Bus SRI (cont’d) Address Range Size Unit Access Type from Read Write cont’d UCB_OTP0_ORIG (UCB) UCB_OTP1_ORIG (UCB) UCB_OTP2_ORIG (UCB) UCB_OTP3_ORIG (UCB) UCB_OTP4_ORIG (UCB) UCB_OTP5_ORIG (UCB) UCB_OTP6_ORIG (UCB) UCB_OTP7_ORIG (UCB) UCB_OTP0_COPY (UCB)
  • Page 14 AURIX™ TC33xEXT Memory Maps (MEMMAP) Table 2 Address Map as seen by Bus Masters on Bus SRI (cont’d) Address Range Size Unit Access Type from Read Write F8710000 F87FFFFF Reserved F8800000 F881FFFF 128 Kbyte Safety Memory Protection Register (CPU0) DLMU Safety Memory Protection registers (CPU0) Safety register protection registers (CPU0) Kernel Reset registers (CPU0) Flash Configuration registers (CPU0)

  • Page 15: Bus Instance Spb

    AURIX™ TC33xEXT Memory Maps (MEMMAP) Bus Instance SPB Table 3 Address Map as seen by Bus Masters on Bus SPB Address Range Size Unit Access Type from Read Write 00000000 0FFFFFFF Reserved 10000000 EFFFFFFF 3584 Mbyte Redirection of SRI ranges (SFIBRIDGE1) Bridge to Bus Segment 00 of SRI (SFIBRIDGE1) F0000000 F00001FF...
  • Page 16 AURIX™ TC33xEXT Memory Maps (MEMMAP) Table 3 Address Map as seen by Bus Masters on Bus SPB (cont’d) Address Range Size Unit Access Type from Read Write F0025000 F00250FF 256 byte FPI slave interface (CONVCTRL) F0025100 F002FFFF Reserved F0030000 F00300FF 256 byte BCU Registers (SBCU) F0030100...

  • Page 17: Bus Instance Bbb

    AURIX™ TC33xEXT Memory Maps (MEMMAP) Table 3 Address Map as seen by Bus Masters on Bus SPB (cont’d) Address Range Size Unit Access Type from Read Write F0200000 F0208FFF 36 Kbyte RAM Area (CAN0) Register Area (CAN0) F0209000 F023FFFF Reserved F0240000 F0241FFF 8 Kbyte...
  • Page 18 AURIX™ TC33xEXT Memory Maps (MEMMAP) Table 4 Address Map as seen by Bus Masters on Bus BBB (cont’d) Address Range Size Unit Access Type from Read Write FA040000 FA0401FF 512 byte FPI slave interface (RIF0) FA040200 FA7FFFFF Reserved FA800000 FA8007FF 2 Kbyte SPU Registers (SPU0) FA800800...

  • Page 19: Revision History

    AURIX™ TC33xEXT Memory Maps (MEMMAP) Revision History Table 5 Revision History Reference Change to Previous Version Comment V0.1.12 – First release for TC33xEXT. – V0.1.13 – No changes. Only version number changed to keep alignment with family – address map. V0.1.14 –...

  • Page 20: Tc33Xext Firmware

    AURIX™ TC33xEXT TC33xEXT Firmware TC33xEXT Firmware This chapter supplements the family documentation with device specific information for TC33xEXT devices. Checker Software exit information for ALL CHECKS PASSED Below the SCU_STMEM3...SCU_STMEM6 registers’ content corresponding to “ALL CHECKS PASSED” result from Checker Software (CHSW) upon different device reset types is shown. Table 6 “ALL CHECKS PASSED”...
  • Page 21 AURIX™ TC33xEXT TC33xEXT Firmware Table 7 Revision History Reference Change to Previous Version Comment Table 6 Footnote added, explaining FW handling after LBIST execution (documentation improvement only, no change in implementation) V1.1.0.1.18 – No functional changes User’s Manual V2.0.0 FW V1.1.0.1.18 2021-02 OPEN MARKET VERSION...

  • Page 22: On-Chip System Connectivity {And Bridges

    AURIX™ TC33xEXT On-Chip System Connectivity {and Bridges} On-Chip System Connectivity {and Bridges} Text with reference to family spec. TC33xEXT Specific IP Configuration Table 8 TC33xEXT specific configuration of DOM Parameter DOM0 Application Reset Application Reset Access only when any Endinit (SCU_WDTCPUxCON0.EI ENDINIT = 0 for any CPUx) Access only when Safety Endinit (SCU_SEICON.EI = 0)

  • Page 23: Tc33Xext Specific Register Set

    AURIX™ TC33xEXT On-Chip System Connectivity {and Bridges} TC33xEXT Specific Register Set Register Address Space Table Table 9 Register Address Space - DOM Module Base Address End Address Note (DOM0) 8FE00000 8FE7FFFF Online Data Acquisition (OLDA) AFE00000 AFE7FFFF Online Data Acquisition (OLDA) DOM0 F8700000 F870FFFF...
  • Page 24 AURIX™ TC33xEXT On-Chip System Connectivity {and Bridges} Table 10 Register Overview - DOM0 (ascending Offset Address) (cont’d) Short Name Description Offset Access Mode Page Address Number Read Write DOM0_ACCEN0 Access Enable Register 0 004F0 32,U,SV 32,SV,SE See Family Spec DOM0_ACCEN1 Access Enable Register 1 004F8 32,U,SV 32,SV,SE See...

  • Page 25: Tc33Xext Specific Registers

    AURIX™ TC33xEXT On-Chip System Connectivity {and Bridges} TC33xEXT Specific Registers 4.3.1 sri slave interface Domain 0 Bridge Control Register DOM0_BRCON Domain 0 Bridge Control Register (00430 Application Reset Value: 0000 0200 OLDAE Field Bits Type Description OLDAEN Online Data Acquisition Enable This bit is used to control trap generated for write accesses to the OLDA address range associated with this domain.

  • Page 26: Revision History

    AURIX™ TC33xEXT On-Chip System Connectivity {and Bridges} r/w MCI has read write connectivity to SCI MCI has only read connectivity to SCI MCI has no connectivity to SCI DMA MIF0 MCI0 r/w r/w SFI F2S MCI1 r/w r/w CPU0 MCI2 r/w r/w CPU1 MCI3...

  • Page 27: Fpi Bus Control Units (Sbcu, Ebcu)

    AURIX™ TC33xEXT FPI Bus Control Units (SBCU, EBCU) This chapter supplements the family documentation with device specific information for TC33xEXT. 4.7.1 TC33xEXT Specific IP Configuration The TC33xEXT includes two FPI Bus instances. Each FPI Bus instances has its dedicated Bus Control Unit: Table 12 Register Address Space - BCU Module...
  • Page 28 AURIX™ TC33xEXT SBCU Control Registers Overview BCU System Registers FPI EDC Registers Access Enable Module ID EDC Alarm Status EDC Alarm Clear Register Register Register Register INT_ACCEN0 BCU_ID BCU_ALSTAT0 BCU_ALCLR0 INT_ACCEN1 BCU_ALSTAT1 BCU_ALCLR1 BCU_ALSTAT2 BCU_ALCLR2 BCU_ALSTAT3 BCU_ALCLR3 FPI Error Generation EDC Control Control Register Register...
  • Page 29 AURIX™ TC33xEXT Table 13 Register Overview - SBCU (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write SBCU_EADD BCU Error Address Capture 0024 U,SV SV,P Application Register Reset Family Spec SBCU_EDAT BCU Error Data Capture 0028 U,SV SV,P...

  • Page 30: Sbcu Control Registers Descriptions

    AURIX™ TC33xEXT Table 13 Register Overview - SBCU (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write SBCU_ACCEN1 Access Enable Register 1 00F8 U,SV SV,SE Application Reset Family Spec SBCU_ACCEN0 Access Enable Register 0 00FC U,SV SV,SE...

  • Page 31: Sbcu Ocds Registers Descriptions

    AURIX™ TC33xEXT Arbiter Priority Register Low SBCU_PRIOL Arbiter Priority Register Low (0018 Application Reset Value: 8854 3210 CPU1 CPU0 RESERVED RESERVED RESERVED SDMMC RESERVED Field Bits Type Description DMA / Cerberus Priority (Index 0) This bit field defines the priority on the SPB for DMA and Cerberus access to the SPB.
  • Page 32 AURIX™ TC33xEXT Field Bits Type Description DMA / Cerberus Trigger Enable FPI Bus transactions with DMA / Cerberus as bus master are enabled for grant trigger event generation. FPI Bus transactions with DMA / Cerberus as bus master are disabled for grant trigger event generation. SDMMC SDMMC Trigger Enable FPI Bus transactions with SDMMC as bus master are enabled for...
  • Page 33 AURIX™ TC33xEXT SBCU Debug Trapped Master Register SBCU_DBGNTT SBCU Debug Trapped Master Register (0044 Debug Reset Value: 0000 FFFF HSMC HSMR SDMM CPU1 CPU0 Field Bits Type Description DMA / Cerberus FPI Bus Master Status The DMA or Cerberus was the FPI bus master. Neither DMA nor Cerberus was the FPI Bus master.
  • Page 34 AURIX™ TC33xEXT Field Bits Type Description Reserved Read as 1 after reset; reading these bits will return the value last written. 31:16 Reserved Read as 1 after reset; reading these bits will return the value last written. BCU EDC Alarm Status Register x The BCU provides one Alarm Status Register bit for each implemented FPI master and FPI slave.
  • Page 35 AURIX™ TC33xEXT Field Bits Type Description ALy (y=07) Alarm y MTU_S, ALy (y=08) Alarm y IOM_S, Alarm y (y=09,13,18- 19,21,24-31) ALy (y=10) Alarm y ASCLIN01_S, ALy (y=11) Alarm y ASCLIN23_S, ALy (y=12) Alarm y ASCLIN45_S, ALy (y=14) Alarm y QSPI0_S, ALy (y=15) Alarm y QSPI1_S,...
  • Page 36 AURIX™ TC33xEXT Field Bits Type Description ALy (y=01) Alarm y CCU6_S, ALy (y=02- Alarm y 06,10,12,14- 18,20-27) ALy (y=07) Alarm y SENT_S, ALy (y=08) Alarm y ETH_S, ALy (y=09) Alarm y EVADC_S, ALy (y=11) Alarm y HSM_S, ALy (y=13) Alarm y CAN0_S, ALy (y=19) Alarm y...
  • Page 37 AURIX™ TC33xEXT Field Bits Type Description Alarm y (y=01,03,07,1 0,15- 20,24,26,28- ALy (y=02) Alarm y P02_S, ALy (y=04) Alarm y P10_S, ALy (y=05) Alarm y P11_S, ALy (y=06) Alarm y P12_S, ALy (y=08) Alarm y P14_S, ALy (y=09) Alarm y P15_S, ALy (y=11) Alarm y...

  • Page 38: Ebcu Control Unit Registers

    AURIX™ TC33xEXT SBCU_ALSTATx (x=3) BCU EDC Alarm Status Register x (0060 +x*4) Application Reset Value: 0000 0000 AL31 AL30 AL29 AL28 AL27 AL26 AL25 AL24 AL23 AL22 AL21 AL20 AL19 AL18 AL17 AL16 AL15 AL14 AL13 AL12 AL11 AL10 AL09 AL08 AL07 AL06 AL05 AL04 AL03 AL02 AL01 AL00 Field Bits Type...
  • Page 39 AURIX™ TC33xEXT • Reset Class 3 -> Application Reset, System Reset, Power-on Reset (see chapter SCU / Reset Types) EBCU Control Registers Overview BCU System Registers FPI EDC Registers Access Enable Module ID EDC Alarm Status EDC Alarm Clear Register Register Register Register...
  • Page 40 AURIX™ TC33xEXT Table 14 Register Overview - EBCU (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write EBCU_EADD BCU Error Address Capture 0024 U,SV SV,P Application Register Reset Family Spec EBCU_EDAT BCU Error Data Capture 0028 U,SV SV,P...

  • Page 41: Ebcu Control Registers Descriptions

    AURIX™ TC33xEXT Table 14 Register Overview - EBCU (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write EBCU_ACCEN1 Access Enable Register 1 00F8 U,SV SV,SE Application Reset Family Spec EBCU_ACCEN0 Access Enable Register 0 00FC U,SV SV,SE...

  • Page 42: Ebcu Ocds Registers Descriptions

    AURIX™ TC33xEXT Field Bits Type Description IOC32P IOC32P Priority (Index 0) This bit field defines the priority on the BBB for IOC32P access to the BBB. RESERVED 7:4, Reserved 11:8, Read as reset value or last written value; should be written with 0. 19:16, 23:20, 31:28...
  • Page 43 AURIX™ TC33xEXT Field Bits Type Description Rearm BCU Breakpoint Logic Writing a 1 to this bit rearms BCU breakpoint logic and sets bit OA = 1. RA is always reads as 0. CONCOM0 Grant and Address Trigger Relation The grant phase trigger condition and the address trigger condition (see CONCOM1) are combined with a logical OR for further control The grant phase trigger condition and the address trigger...
  • Page 44 AURIX™ TC33xEXT Field Bits Type Description ONBOS0 Op code Signal Status Trigger Condition A signal status trigger is generated for all FPI Bus op-codes except a “no operation” op-code A signal status trigger is generated if the FPI Bus op-code matches the op-code as defined in DBBOS.OPC ONBOS1 Supervisor Mode Signal Trigger Condition...
  • Page 45 AURIX™ TC33xEXT Field Bits Type Description IOC32P IOC32P Trigger Enable FPI Bus transactions with IOC32P as bus master are enabled for grant trigger event generation FPI Bus transactions with IOC32P as bus master are disabled for grant trigger event generation IOC32E IOC32E Grant Trigger Enable FPI Bus transactions with IOC32E as bus master are enabled for...
  • Page 46 AURIX™ TC33xEXT Field Bits Type Description IOC32P IOC32P FPI Bus Master Status This bit indicates whether the IOC32P was FPI Bus master when the break trigger event occurred. The IOC32P was the FPI bus master. The IOC32P was not the FPI Bus master. IOC32E IOC32E FPI Bus Master Status This bit indicates whether the IOC32E was FPI Bus master when the...
  • Page 47 AURIX™ TC33xEXT Field Bits Type Description ALy (y=00) Alarm y EBCU_S, ALy (y=01) Alarm y MCDS_S, ALy (y=02) Alarm y AGBT_S, ALy (y=03- Alarm y 05,09- 15,17,20-31) ALy (y=06) Alarm y EMEM_XTMRAM_S, ALy (y=07) Alarm y EMEM_CTRL_S, ALy (y=08) Alarm y EMEM0_S, ALy (y=16) Alarm y...
  • Page 48 AURIX™ TC33xEXT EBCU_ALSTATx (x=2) BCU EDC Alarm Status Register x (0060 +x*4) Application Reset Value: 0000 0000 AL31 AL30 AL29 AL28 AL27 AL26 AL25 AL24 AL23 AL22 AL21 AL20 AL19 AL18 AL17 AL16 AL15 AL14 AL13 AL12 AL11 AL10 AL09 AL08 AL07 AL06 AL05 AL04 AL03 AL02 AL01 AL00 Field Bits Type...

  • Page 49: Connectivity

    AURIX™ TC33xEXT Field Bits Type Description ALy (y=19) Alarm y IOC32E_M, ALy (y=22) Alarm y SFI_S2F_M, 4.7.4 Connectivity 4.7.4.1 SBCU Connectivity Table 15 Connections of SBCU Interface Signals connects Description SBCU:INT INT:sbcu_INT Bus Control Unit SPB Service Request 4.7.4.2 EBCU Connectivity Table 16 Connections of EBCU Interface Signals...

  • Page 50: Cpu Subsystem (Cpu)

    AURIX™ TC33xEXT CPU Subsystem (CPU) CPU Subsystem (CPU) This chapter describes the CPU subsystem module of the TC33xEXT. TC33xEXT Specific Configuration No product specific configuration for CPU TC33xEXT Specific Register Set Register Address Space Table Table 18 Register Address Space - CPU Module Base Address End Address...
  • Page 51 AURIX™ TC33xEXT CPU Subsystem (CPU) Register Overview Tables of CPU Table 19 Register Overview - CPU0 (ascending Offset Address) Short Name Long Name Offset Page Address Number CPU0_FLASHCON0 CPUx Flash Configuration Register 0 01100 CPU0_FLASHCON1 CPUx Flash Configuration Register 1 01104 Family Spec...
  • Page 52 AURIX™ TC33xEXT CPU Subsystem (CPU) Table 19 Register Overview - CPU0 (ascending Offset Address) (cont’d) Short Name Long Name Offset Page Address Number CPU0_SFR_SPROT_A CPUx Safety Protection Register Access Enable Register A 0E100 CCENA_W Family Spec CPU0_SFR_SPROT_A CPUx Safety Protection Region Access Enable Register B 0E104 CCENB_W Family...
  • Page 53 AURIX™ TC33xEXT CPU Subsystem (CPU) Table 19 Register Overview - CPU0 (ascending Offset Address) (cont’d) Short Name Long Name Offset Page Address Number CPU0_SEGEN CPUx SRI Error Generation Register 11030 Family Spec CPU0_TASK_ASI CPUx Task Address Space Identifier Register 18004 Family Spec CPU0_PMA0...
  • Page 54 AURIX™ TC33xEXT CPU Subsystem (CPU) Table 19 Register Overview - CPU0 (ascending Offset Address) (cont’d) Short Name Long Name Offset Page Address Number CPU0_PCON1 CPUx Program Control 1 19204 Family Spec CPU0_PCON2 CPUx Program Control 2 19208 Family Spec CPU0_PCON0 CPUx Program Control 0 1920C Family...
  • Page 55 AURIX™ TC33xEXT CPU Subsystem (CPU) Table 19 Register Overview - CPU0 (ascending Offset Address) (cont’d) Short Name Long Name Offset Page Address Number CPU0_CPRy_L CPUx Code Protection Range y Lower Bound Register 1D000 +y*8 (y=0-9) Family Spec CPU0_CPRy_U CPUx Code Protection Range y Upper Bound Register 1D004 +y*8 (y=0-9)
  • Page 56 AURIX™ TC33xEXT CPU Subsystem (CPU) Table 19 Register Overview - CPU0 (ascending Offset Address) (cont’d) Short Name Long Name Offset Page Address Number CPU0_TPS_EXTIM_C CPUx Exception Timer Class Enable Register 1E450 LASS_EN Family Spec CPU0_TPS_EXTIM_S CPUx Exception Timer Status Register 1E454 Family Spec...
  • Page 57 AURIX™ TC33xEXT CPU Subsystem (CPU) Table 19 Register Overview - CPU0 (ascending Offset Address) (cont’d) Short Name Long Name Offset Page Address Number CPU0_SWEVT CPUx Software Debug Event 1FD10 Family Spec CPU0_TRIG_ACC CPUx TriggerAddressx 1FD30 Family Spec CPU0_DMS CPUx Debug Monitor Start Address 1FD40 Family Spec...
  • Page 58 AURIX™ TC33xEXT CPU Subsystem (CPU) Table 19 Register Overview - CPU0 (ascending Offset Address) (cont’d) Short Name Long Name Offset Page Address Number CPU0_ICR CPUx Interrupt Control Register 1FE2C Family Spec CPU0_FCX CPUx Free CSA List Head Pointer 1FE38 Family Spec CPU0_LCX CPUx Free CSA List Limit Pointer...
  • Page 59 AURIX™ TC33xEXT CPU Subsystem (CPU) Table 20 Register Overview - CPU1 (ascending Offset Address) (cont’d) Short Name Long Name Offset Page Address Number CPU1_KRST1 CPUx Reset Register 1 0D004 Family Spec CPU1_KRSTCLR CPUx Reset Clear Register 0D008 Family Spec CPU1_SPR_SPROT_R CPUx Safety Protection SPR Region Lower Address Register i 0E000 +i*10 GNLAi...
  • Page 60 AURIX™ TC33xEXT CPU Subsystem (CPU) Table 20 Register Overview - CPU1 (ascending Offset Address) (cont’d) Short Name Long Name Offset Page Address Number CPU1_DLMU_SPROT CPUx Safety Protection Region DLMU Write Access Enable 0E208 +i*10 _RGNACCENAi_W Register Ai Family (i=0-7) Spec CPU1_DLMU_SPROT CPUx Safety Protection Region DLMU Write Access Enable 0E20C...
  • Page 61 AURIX™ TC33xEXT CPU Subsystem (CPU) Table 20 Register Overview - CPU1 (ascending Offset Address) (cont’d) Short Name Long Name Offset Page Address Number CPU1_SMACON CPUx SIST Mode Access Control Register 1900C Family Spec CPU1_DSTR CPUx Data Synchronous Trap Register 19010 Family Spec CPU1_DATR...
  • Page 62 AURIX™ TC33xEXT CPU Subsystem (CPU) Table 20 Register Overview - CPU1 (ascending Offset Address) (cont’d) Short Name Long Name Offset Page Address Number CPU1_FPU_TRAP_CO CPUx Trap Control Register 1A000 Family Spec CPU1_FPU_TRAP_PC CPUx Trapping Instruction Program Counter Register 1A004 Family Spec CPU1_FPU_TRAP_OP CPUx Trapping Instruction Opcode Register...
  • Page 63 AURIX™ TC33xEXT CPU Subsystem (CPU) Table 20 Register Overview - CPU1 (ascending Offset Address) (cont’d) Short Name Long Name Offset Page Address Number CPU1_DPRE_y CPUx Data Protection Read Enable Register Set y 1E050 +(y- (y=4-5) 4)*4 Family Spec CPU1_DPWE_y CPUx Data Protection Write Enable Register Set y 1E060 +(y- (y=4-5)
  • Page 64 AURIX™ TC33xEXT CPU Subsystem (CPU) Table 20 Register Overview - CPU1 (ascending Offset Address) (cont’d) Short Name Long Name Offset Page Address Number CPU1_CCNT CPUx CPU Clock Cycle Count 1FC04 Family Spec CPU1_ICNT CPUx Instruction Count 1FC08 Family Spec CPU1_M1CNT CPUx Multi-Count Register 1 1FC0C Family...
  • Page 65 AURIX™ TC33xEXT CPU Subsystem (CPU) Table 20 Register Overview - CPU1 (ascending Offset Address) (cont’d) Short Name Long Name Offset Page Address Number CPU1_PSW CPUx Program Status Word 1FE04 Family Spec CPU1_PC CPUx Program Counter 1FE08 Family Spec CPU1_SYSCON CPUx System Configuration Register 1FE14 Family Spec...

  • Page 66: Tc33Xext Specific Registers

    AURIX™ TC33xEXT CPU Subsystem (CPU) TC33xEXT Specific Registers 5.3.1 SRI slave interface for SFR+CSFR CPUx Flash Configuration Register 0 Software may program a Flash Prefetch Buffer with a master tag identifier stored in Flash Configuration Register If a CPU instance does not have a local PFlash bank then the FLASHCON0 register associated with that instance will have no functionality.

  • Page 67: Revision History

    AURIX™ TC33xEXT CPU Subsystem (CPU) Revision History Table 22 Revision History Reference Change to Previous Version Comment V1.1.16 No change V1.1.17 No change V1.1.18 No change V1.1.19 No change V1.1.20 Page Change index variable from 'x' to intended 'i' for registers SPR_SPROT_RGNACCENAi_R and SPR_SPROT_RGNACCENBi_R to remove confusion with CPU instance variable.

  • Page 68: Non Volatile Memory (Nvm) Subsystem

    AURIX™ TC33xEXT Non Volatile Memory (NVM) Subsystem Non Volatile Memory (NVM) Subsystem Overview The Non Volatile Memory (NVM) Subsystem comprises of the Data Memory Unit (DMU), Program Flash Interface (PFI), and Non Volatile Memory module (comprising of the Flash Standard Interface (FSI), Program and Data Flash memories and Program Flash Read Write buffer (PFRWB)).
  • Page 69 AURIX™ TC33xEXT Non Volatile Memory (NVM) Subsystem CPUn SRI SIF PFIn BROM PFRWBn FSI RAM FSI REG DFRWB0 DFRWB1 Figure 4 Non Volatile Memory (NVM) Subsystem The purpose of the PFLASH NVM is: • One or more PFLASH banks stores program code and data constants. •...
  • Page 70 AURIX™ TC33xEXT Non Volatile Memory (NVM) Subsystem • Write protection is enabled/disabled with a Flash Module sector based granularity. Safety Layer • Master specific read access protection to each Flash Module (Bank). • Master specific read and write access control to individual Special Function Registers (SFRs). •...

  • Page 71: Revision History

    AURIX™ TC33xEXT Non Volatile Memory (NVM) Subsystem Revision History Table 23 Revision History Reference Change to Previous Version Comment V2.0.3 Created to form a concise introduction chapter for the appendices V2.0.4 No Changes. V2.0.5 No Changes. V2.0.6 No Changes. V2.0.7 No Changes.

  • Page 72: Data Memory Unit (Dmu)

    AURIX™ TC33xEXT Data Memory Unit (DMU) This chapter supplements the family documentation with the device specific information for TC33xEXT. 6.3.1 TC33xEXT Specific Register Set Register Address Space Table Table 24 Register Address Space - PMU Module Base Address End Address Note F8038000 F803FFFF...
  • Page 73 AURIX™ TC33xEXT Table 27 Register Overview - DMU (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write DMU_HF_CONTR Flash Control Register 0000014 U,SV P,SV,E Application Reset Family Spec DMU_HF_OPERA Flash Operation Register 0000018 U,SV System Reset...
  • Page 74 AURIX™ TC33xEXT Table 27 Register Overview - DMU (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write DMU_HF_PSTAT Power Status Register 0000060 U,SV Application Reset Family Spec DMU_HF_PCONT Power Control Register 0000064 U,SV P,SV Application...
  • Page 75 AURIX™ TC33xEXT Table 27 Register Overview - DMU (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write DMU_HP_PROCO PFLASH Bank i Protection 0010000 U,SV See Family Spec See NPi0 Configuration 0 Family (i=0) Spec DMU_HP_PROCO...
  • Page 76 AURIX™ TC33xEXT Table 27 Register Overview - DMU (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write DMU_HP_PROCO PFLASH Bank i WOP 0010088 U,SV See Family Spec See NWOPi2 Configuration 2 Family (i=0) Spec DMU_HP_PROCO...
  • Page 77 AURIX™ TC33xEXT Table 27 Register Overview - DMU (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write DMU_SF_ERRSR HSM Error Status Register 0020034 Application Reset Family Spec DMU_SF_CLRE HSM Clear Error Register 0020038 Application Reset...

  • Page 78: Tc33Xext Specific Registers

    AURIX™ TC33xEXT Table 27 Register Overview - DMU (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write DMU_SP_PROCO HSM Code OTP Protection 0030014 U,SV See Family Spec See NHSMCOTP1 Configuration Family Spec DMU_SP_PROCO HSM Interface Protection 0030040...
  • Page 79 AURIX™ TC33xEXT Field Bits Type Description D1BUSY Data Flash Bank 1 Busy HW-controlled status flag. Indication of busy state of DFLASH bank 1 because of active execution of an operation; DF1 busy state is also indicated during Flash startup after reset or in sleep mode;...
  • Page 80 AURIX™ TC33xEXT Field Bits Type Description PFPAGE Program Flash in Page Mode HW-controlled status flag. Set with Enter Page Mode for Flash, cleared with Write Page command This bit is not set by “Enter Page Mode” initiated by the HSM interface. Note: Read accesses are allowed while in page mode.
  • Page 81 AURIX™ TC33xEXT Field Bits Type Description PRODISEC Erase Counter Priority Protection Disabled The protection configured by UCB_ECPRIO_ORIG and UCB_ECPRIO_COPY was successfully disabled by supplying the correct password to “Disable Protection”. Note: Cleared with command "Resume Protection". PRODISBMHD 4 BMHD Protection Disabled The protection configured by UCB_BMHD0_ORIG and UCB_BMHD0_COPY was successfully disabled by supplying the correct password to “Disable Protection”.
  • Page 82 AURIX™ TC33xEXT Tuning Protection Configuration DMU_HF_PROCONTP Tuning Protection Configuration (0000084 Reset Value: Table 28 CPU0 SWAPEN DDIS Field Bits Type Description Tuning Protection This bit indicates whether tuning protection is installed or not. Tuning protection is not configured. Tuning protection is configured and installed, if correctly confirmed.

  • Page 83: Connectivity

    AURIX™ TC33xEXT Table 28 Reset Values of DMU_HF_PROCONTP Reset Type Reset Value Note Application Reset 0000 0000 CFS Value 0000 0000 6.3.3 Connectivity Table 29 Connections of DMU Interface Signals connects Description DMU:HOST_INT INT:dmu.HOST_INT PMU Host Service Request DMU:FSI_INT INT:dmu.FSI_INT PMU FSI Service Request 6.3.4 Revision History...

  • Page 84: Non Volatile Memory (Nvm)

    AURIX™ TC33xEXT Non Volatile Memory (NVM) This chapter supplements the family documentation with the device specific information for TC33xEXT. 6.4.1 TC33xEXT Specific Register Set Register Address Space Table Table 31 Register Address Space - FSI Module Base Address End Address Note F8030000 F80300FF...

  • Page 85: Connectivity

    AURIX™ TC33xEXT Table 34 Register Overview - PFI (ascending Offset Address) Short Name Long Name Offset Page Address Number PFI0_ECCR ECC Read Register 000000 Family Spec PFI0_ECCS ECC Status Register 000020 Family Spec PFI0_SBABRECORDx SBAB Record x 002000 +x*20 (x=0-16) Family Spec PFI0_DBABRECORDx...

  • Page 86: Local Memory Unit (Lmu)

    AURIX™ TC33xEXT Local Memory Unit (LMU) Local Memory Unit (LMU) This device doesn’t contain a LMU module. User’s Manual V2.0.0 2021-02 OPEN MARKET VERSION...
  • Page 87 AURIX™ TC33xEXT Default Application Memory (LMU_DAM) Default Application Memory (LMU_DAM) This device doesn’t contain LMU_DAM. User’s Manual V2.0.0 LMU_DAM 2021-02 OPEN MARKET VERSION...

  • Page 88: System Control Unit (Scu)

    AURIX™ TC33xEXT System Control Unit (SCU) System Control Unit (SCU) This chapter describes the System Control Unit (short SCU) Module of the TC33xEXT. TC33xEXT Specific IP Configuration Table 36 TC33xEXT specific configuration of SCU Parameter Number of WDT linked to the number of CPU Name of the ssw value After SSW execution CFS value for DTSCBGOCTRL register...

  • Page 89: Tc33Xext Specific Register Set

    AURIX™ TC33xEXT System Control Unit (SCU) TC33xEXT Specific Register Set The address space for the module registers is defined in Register Address Space - SCU. Table 37 Register Address Space - SCU Module Base Address End Address Note F0036000 F00363FF SCU: Connections to FPI/BPI bus Table 38 Register Overview - SCU (ascending Offset Address)
  • Page 90 AURIX™ TC33xEXT System Control Unit (SCU) Table 38 Register Overview - SCU (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write SCU_CCUCON1 CCU Clock Control Register 0034 U,SV SV,SE,P0 System Reset Family Spec SCU_FDR Fractional Divider Register...
  • Page 91 AURIX™ TC33xEXT System Control Unit (SCU) Table 38 Register Overview - SCU (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write SCU_ESROCFG ESR Output Configuration 0078 U,SV SV,E,P0 System Reset Register Family Spec SCU_SYSCON System Control Register...
  • Page 92 AURIX™ TC33xEXT System Control Unit (SCU) Table 38 Register Overview - SCU (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write SCU_PMCSR2 Power Management Control 00D0 U,SV SE,CE2,SV, Application and Status Register Reset Family Spec...
  • Page 93 AURIX™ TC33xEXT System Control Unit (SCU) Table 38 Register Overview - SCU (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write SCU_TRAPCLR Trap Clear Register 012C U,SV U,SV,P0 System Reset Family Spec SCU_TRAPDIS0 Trap Disable Register 0 0130...
  • Page 94 AURIX™ TC33xEXT System Control Unit (SCU) Table 38 Register Overview - SCU (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write SCU_PDISC Pad Disable Control 018C U,SV SV,E,P0 System Reset Register Family Spec Reserved (0020 Byte)
  • Page 95 AURIX™ TC33xEXT System Control Unit (SCU) Table 38 Register Overview - SCU (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write SCU_FMR Flag Modification Register 0224 U,SV U,SV,P0 Application Reset Family Spec SCU_PDRR Pattern Detection Result 0228...
  • Page 96 AURIX™ TC33xEXT System Control Unit (SCU) Table 38 Register Overview - SCU (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write SCU_SEICON0 Safety ENDINIT Control 02B4 U,SV U,SV,32,P1 Application Register 0 Reset Family Spec SCU_SEICON1...

  • Page 97: Tc33Xext Specific Registers

    AURIX™ TC33xEXT System Control Unit (SCU) TC33xEXT Specific Registers 9.3.1 SCU: Connections to FPI/BPI bus LCL CPU0 and CPU2 Control Register Provides control for CPU0and CPU2 Lockstep Comparator Logic blocks. SCU_LCLCON0 LCL CPU0 and CPU2 Control Register (0134 Reset Value: Table 39 LSEN0 Field...
  • Page 98 AURIX™ TC33xEXT System Control Unit (SCU) SCU_LCLCON1 LCL CPU1 and CPU3 Control Register (0138 Reset Value: Table 40 Field Bits Type Description Reserved in this product 14:1, Reserved 30:17 Reserved in this product Reserved Table 40 Reset Values of SCU_LCLCON1 Reset Type Reset Value Note...
  • Page 99 AURIX™ TC33xEXT System Control Unit (SCU) Field Bits Type Description LCLT1 LCL1 Lockstep Test Fault injection for LCL1. Reads as zero. No action Inject single fault in LCL1 PLCLT0 PFI0 Lockstep Test Fault injection for PFI0 lockstep. Reads as zero. No action Inject single fault in PFI0 lockstep PLCLT1...
  • Page 100 AURIX™ TC33xEXT System Control Unit (SCU) Table 41 Reset Values of SCU_LBISTCTRL2 Reset Type Reset Value Note System Reset 0000 0000 CFS Value 0000 003C Overlay Enable Register SCU_OVCENABLE Overlay Enable Register (01E0 Application Reset Value: 0000 0000 OVEN1 OVEN0 Field Bits Type...
  • Page 101 AURIX™ TC33xEXT System Control Unit (SCU) Overlay Control Register SCU_OVCCON Overlay Control Register (01E4 Application Reset Value: 0000 0000 POVC OVCO DCINV OVSTR OVSTP CSEL1 CSEL0 Field Bits Type Description CSEL0 CPU Select 0 Return 0 if read. CPU0 not affected, Action selected by OVSTRT, OVSTP, DCINVAL bits, set by the same register write access, is applied to CPU0.
  • Page 102 AURIX™ TC33xEXT System Control Unit (SCU) Field Bits Type Description OVCONF Overlay Configured Overlay configured status bit This bit may be used as handshake bit between a debug device (via JTAG interface and Cerberus) and CPU(s). Overlay is not configured or it has been already started Overlay block control registers are configured and ready for overlay start POVCONF...
  • Page 103 AURIX™ TC33xEXT System Control Unit (SCU) Field Bits Type Description Reset Request Trigger Reset Status for SMU (See SMU section for SMU trigger sources, including Watchdog Timers) The last reset was not requested by this reset trigger The last reset was requested by this reset trigger Reset Request Trigger Reset Status for SW The last reset was not requested by this reset trigger The last reset was requested by this reset trigger...
  • Page 104 AURIX™ TC33xEXT System Control Unit (SCU) Field Bits Type Description Reset Request Trigger Reset Status for Supply Watchdog (SWD) The Supply Watchdog trigger is described in Power Management Controller “Supply Monitoring” chapter This reset trigger has not occurred since the last clear (by RSTCON2.CLRC) This reset trigger has occurred since the last clear (by RSTCON2.CLRC)
  • Page 105 AURIX™ TC33xEXT System Control Unit (SCU) Table 42 Reset Values of SCU_RSTSTAT Reset Type Reset Value Note Cold PowerOn 0XX1 0000 RSTSTAT Reset Cold PowerOn 1001 0000 RSTSTAT (Triggered by LVD Reset) Reset Reset Configuration Register SCU_RSTCON Reset Configuration Register (0058 Reset Value: Table 43...
  • Page 106 AURIX™ TC33xEXT System Control Unit (SCU) Field Bits Type Description SW Reset Request Trigger Reset Configuration This bit field defines which reset is generated by a reset request trigger from software reset. No reset is generated for a trigger of software reset A System Reset is generated for a trigger of Software reset An Application Reset is generated for a trigger of Software reset Reserved, do not use this combination...
  • Page 107 AURIX™ TC33xEXT System Control Unit (SCU) Field Bits Type Description STM0DIS STM0 Disable Reset This bit field defines if an Application Reset leads to an reset for the STM0. An Application Reset resets the STM0 An Application Reset has no effect for the STM0 STM1DIS STM1 Disable Reset This bit field defines if an Application Reset leads to an reset for the...
  • Page 108 AURIX™ TC33xEXT System Control Unit (SCU) Trap Disable Register 0 SCU_TRAPDIS0 Trap Disable Register 0 (0130 Application Reset Value: FFFF FFFF CPU3xT CPU2xT CPU1S CPU1T CPU1E CPU1E CPU0S CPU0T CPU0E CPU0E RAP2T SR1T SR0T RAP2T SR1T SR0T Field Bits Type Description CPU0ESR0T Disable Trap Request ESR0T on CPU0...

  • Page 109: Connectivity

    AURIX™ TC33xEXT System Control Unit (SCU) Connectivity Table 44 Connections of SCU Interface Signals connects Description SCU:CBS_ENDINIT_DIS from CBS:ocds_oc(3) Watchdog ENDINIT disable from Cerberus SCU:CBS_WDT_SUSP from CBS:ocds_wdtsus Watchdog suspend from Cerberus SCU:EMGSTOP_PORT_A from SMU:FSPSCU Emergency stop Port Pin A input request SCU:EMGSTOP_PORT_B from P21.2:IN Emergency stop Port Pin B input request...
  • Page 110 AURIX™ TC33xEXT System Control Unit (SCU) Table 44 Connections of SCU (cont’d) Interface Signals connects Description SCU:E_PDOUT(6) GPT120:CAPINB ERU PDOUTn output (MSB is PDOUT7 and LSB is PDOUT0) SCU:E_REQ0(0) from P15.4:IN ERU Channel 0 input X; x=0-5, where 0 is input A and 5 is input F.

  • Page 111: Revision History

    AURIX™ TC33xEXT System Control Unit (SCU) Table 44 Connections of SCU (cont’d) Interface Signals connects Description SCU:E_REQ6(1) from TC33xEXT:ESR0 ERU Channel 6 input X; x=0-5, where 0 is input A and 5 is input F. SCU:E_REQ6(3) from P11.10:IN ERU Channel 6 input X; x=0-5, where 0 is input A and 5 is input F.
  • Page 112 AURIX™ TC33xEXT System Control Unit (SCU) Table 45 Revision History (cont’d) Reference Change to Previous Version Comment Page 24 Revision History cleanup and update. V2.1.23 Page 1 LBISTCTRL register configuration corrected. Page LBISTCTRL2 added at specific registers section. Page 10 V2.1.24 Page 10 Updated Cold PowerOn Reset Value of LCLCONx.

  • Page 113: Clocking System

    AURIX™ TC33xEXT Clocking System Clocking System Device specific information about the clocking system is contained in the SCU chapter as both modules share a common bus interface. User’s Manual 10-1 V2.0.0 CCUV2.0.29 2021-02 OPEN MARKET VERSION...

  • Page 114: Power Management System (Pms)

    AURIX™ TC33xEXT Power Management System (PMS) Power Management System (PMS) This chapter describes the Power Management System (PMS) Module of the TC33xEXT. 11.1 TC33xEXT Specific IP Configuration Table 46 TC33xEXT specific configuration of PMS Parameter CFS value for the PMSWCR4 register 02000020 User’s Manual 11-1...

  • Page 115: Tc33Xext Specific Register Set

    AURIX™ TC33xEXT Power Management System (PMS) 11.2 TC33xEXT Specific Register Set The PMS related SCU registers are specified in the SCU section of this appendix. Table 47 Register Address Space - PMS Module Base Address End Address Note (PMS) F0240000 F0241FFF F0248000 F02481FF...
  • Page 116 AURIX™ TC33xEXT Power Management System (PMS) Table 48 Register Overview - PMS (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write PMS_PMSIEN PMS Interrupt Enable 0074 U,SV SV,SE,P See Family Spec See Register Family Spec...
  • Page 117 AURIX™ TC33xEXT Power Management System (PMS) Table 48 Register Overview - PMS (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write PMS_PMSWSTAT Standby and Wake-up 00D4 U,SV LVD Reset Status Register Family Spec PMS_PMSWSTAT Standby and Wake-up...
  • Page 118 AURIX™ TC33xEXT Power Management System (PMS) Table 48 Register Overview - PMS (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write PMS_EVRSDCTRL EVRC SD Control Register 9 012C U,SV SV,SE,P See Family Spec See Family Spec PMS_EVRSDCTRL...
  • Page 119 AURIX™ TC33xEXT Power Management System (PMS) Table 48 Register Overview - PMS (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write PMS_MONBISTS SMU_stdby BIST Status 0190 U,SV See Family Spec See Register Family Spec PMS_MONBISTC...

  • Page 120: Connectivity

    AURIX™ TC33xEXT Power Management System (PMS) 11.3 TC33xEXT Specific Registers 11.3.1 FPI slave interface 11.4 Connectivity Table 49 Connections of PMS Interface Signals connects Description PMS:DCDCSYNCO P32.4:HWOUT(0) DC-DC synchronization output P32.4:ALT(2) PMS:ESR0PORST TC33xEXT:ESR0 ESR0 control output during PORST activation PMS:ESR0WKP from TC33xEXT:ESR0 ESR0 pin input PMS:ESR1WKP...
  • Page 121 AURIX™ TC33xEXT Power Management System (PMS) Table 50 Revision History (cont’d) Reference Change to Previous Version Comment – No functional changes. V2.2.32 No functional changes. V2.2.33 – No functional changes. V2.2.34 – No functional changes. User’s Manual 11-8 V2.0.0 PMSV2.2.34 2021-02 OPEN MARKET VERSION...

  • Page 122: Power Management System For Low-End (Pmsle)

    AURIX™ TC33xEXT Power Management System for Low-End (PMSLE) Power Management System for Low-End (PMSLE) This device doesn’t contain a PMSLE module. User’s Manual 12-1 V2.0.0 PMSLE 2021-02 OPEN MARKET VERSION...

  • Page 123: Memory Test Unit (Mtu)

    AURIX™ TC33xEXT Memory Test Unit (MTU) Memory Test Unit (MTU) For the generic description of the Memory Test Unit (MTU) and the SRAM Support Hardware (SSH), please refer to the platform chapter. 13.1 TC33xEXT Specific IP Configuration There is no device specific IP configuration. MTU+SSH is generic across all derivates in the platforms. Only the SSH instances vary.

  • Page 124: Tc33Xext Specific Register Set

    AURIX™ TC33xEXT Memory Test Unit (MTU) 13.3 TC33xEXT Specific Register Set Register Address Space Table Table 51 Register Address Space - MTU Module Base Address End Address Note F0060000 F006FFFF FPI slave interface Register Overview Table Table 52 Register Overview - MTU (ascending Offset Address) Short Name Long Name Offset...

  • Page 125: Tc33Xext Specific Registers

    AURIX™ TC33xEXT Memory Test Unit (MTU) Table 52 Register Overview - MTU (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write MTU_MCi_MCON MBIST Control Register 1004 U,SV,16 SV,SE,P,16 Application TROL Reset Family (i=0-95) Spec MTU_MCi_MSTA...
  • Page 126 AURIX™ TC33xEXT Memory Test Unit (MTU) MTU_MEMTESTi (i=0) Memory MBIST Enable Register i (0010 +i*4) Application Reset Value: 0000 0000 RES31 RES30 RES29 RES28 RES27 RES26 RES25 RES24 RES23 RES22 RES21 RES20 RES19 RES18 RES17 RES16 CPU1_ CPU0_ CPU1_ CPU1_ CPU1_ CPU1_ CPU0_...
  • Page 127 AURIX™ TC33xEXT Memory Test Unit (MTU) Field Bits Type Description CPU1_DLMU_ CPU1 STANDBY DLMU SSH instance Enable STBY_EN SSH instance is disabled SSH instance is enabled MTU_MEMTESTi (i=1) Memory MBIST Enable Register i (0010 +i*4) Application Reset Value: 0000 0000 SPU_C SPU_B EMEM...
  • Page 128 AURIX™ TC33xEXT Memory Test Unit (MTU) Field Bits Type Description SPU_CONFIG0 SPU CONFIG0 memory SSH instance Enable SSH instance is disabled SSH instance is enabled MCAN10_EN MCAN10 memory SSH instance Enable SSH instance is disabled SSH instance is enabled 1) Please refer to separate section related to handling of the large DMEM on this device. MTU_MEMTESTi (i=2) Memory MBIST Enable Register i (0010...
  • Page 129 AURIX™ TC33xEXT Memory Test Unit (MTU) Field Bits Type Description SCR_XRAM_E SCR XRAM SSH instance Enable SSH instance is disabled SSH instance is enabled SCR_RAMINT_ SCR Internal RAM SSH instance Enable SSH instance is disabled SSH instance is enabled GIGETH_RX_E Gigabit Ethernet RX SSH instance Enable SSH MSTATUS.DONE = 0 SSH MSTATUS.DONE = 1...

  • Page 130: Memmap Implementation

    AURIX™ TC33xEXT Memory Test Unit (MTU) 13.4.2 MEMMAP Implementation The Memory Mapping Enable register MEMMAP has configurable control bits to select memory-mapped test mode for each CPU memory. Cache and Scratchpad memories are physically implemented as a single RAM, but this register function assumes two separate logical RAM partitions.
  • Page 131 AURIX™ TC33xEXT Memory Test Unit (MTU) Field Bits Type Description CPU0_PCMAP 2 CPU0 PCACHE Mapping Normal cache function Memory-mapped CPU0_PTMAP 3 CPU0 PTAG Mapping Read only. Mirrors the state of CPU0_PCMAP. CPU P-cache memories may only be mapped simultaneously. Normal cache function Memory-mapped Reserved - Res Reserved.

  • Page 132: Memstat Implementation

    AURIX™ TC33xEXT Memory Test Unit (MTU) 13.4.3 MEMSTAT Implementation The Memory Status Registers MEMSTATx have an implemented bit for each security relevant RAM. The Data- and Program- Cache and Scratchpad memories are physically implemented as a single RAM with a single MBIST.
  • Page 133 AURIX™ TC33xEXT Memory Test Unit (MTU) Field Bits Type Description CPU0_PTAG_ CPU0 PTAG MBIST AutoInitialize Underway This bit indicates whether an automatic data initialization has been triggered by a change of state of MEMTEST.MEMxEN or MEMxMAP but that the intialization sequence has not yet completed. MBIST not running autoinitialize MBIST running autoinitialize Reserved - Res...
  • Page 134 AURIX™ TC33xEXT Memory Test Unit (MTU) MTU_MEMSTATi (i=1) Memory Status Register i (0038 +i*4) Application Reset Value: 0000 0000 CPU1_ CPU0_ DMEM DMEM 1_AIU 1_AIU Field Bits Type Description Reserved - Res Reserved. Not used in this product. CPU0_DMEM1 CPU0 DMEM1 Partial AutoInitialize of Cache Partition Underway _AIU SSH instance is disabled SSH instance is enabled...

  • Page 135: Memdone Implementation

    AURIX™ TC33xEXT Memory Test Unit (MTU) Field Bits Type Description Reserved - Res Reserved. Not used in this product. Reserved - Res Reserved. Not used in this product. Reserved - Res Reserved. Not used in this product. Reserved - Res Reserved.
  • Page 136 AURIX™ TC33xEXT Memory Test Unit (MTU) Field Bits Type Description CPU0_DMEM_ CPU0 DMEM Test Done Status DONE SSH MSTATUS.DONE = 0 SSH MSTATUS.DONE = 1 RESz (z=10- Reserved Reserved. Not used in this product. CPU0_DTAG_ CPU0 DTAG Test Done Status DONE SSH MSTATUS.DONE = 0 SSH MSTATUS.DONE = 1...
  • Page 137 AURIX™ TC33xEXT Memory Test Unit (MTU) MTU_MEMDONEi (i=1) Memory Test Done Status Register i (0050 +i*4) Application Reset Value: FFFF FFFF SPU_C SPU_B MCAN EMEM ONFIG UFFER RES31 10_DO RES29 RES28 RES27 RES26 RES25 RES24 RES23 RES22 RES21 RES20 RES18 _XTM_ 0_DO 0_DO...
  • Page 138 AURIX™ TC33xEXT Memory Test Unit (MTU) Field Bits Type Description MCAN10_DON MCAN10 memory Test Done Status SSH MSTATUS.DONE = 0 SSH MSTATUS.DONE = 1 1) Please refer to separate section related to handling of the large DMEM on this device. MTU_MEMDONEi (i=2) Memory Test Done Status Register i (0050...

  • Page 139: Memfda Implementation

    AURIX™ TC33xEXT Memory Test Unit (MTU) Field Bits Type Description GIGETH_TX_D Gigabit Ethernet TX memoryTest Done Status SSH MSTATUS.DONE = 0 SSH MSTATUS.DONE = 1 SDMMC_DON SDMMC memoryTest Done Status SSH MSTATUS.DONE = 0 SSH MSTATUS.DONE = 1 HSPDM_RAM_ HDSPDM RAM Test Done Status DONE SSH MSTATUS.DONE = 0 SSH MSTATUS.DONE = 1...
  • Page 140 AURIX™ TC33xEXT Memory Test Unit (MTU) Field Bits Type Description RESz (z=10- Reserved Reserved. Not used in this product. CPU0_DTAG_ CPU0 DTAG Test FDA Status SSH MSTATUS.FDA = 0 SSH MSTATUS.FDA = 1 CPU0_PMEM_ CPU0 PMEM Test FDA Status SSH MSTATUS.FDA = 0 SSH MSTATUS.FDA = 1 CPU0_PTAG_F CPU0 PTAG Test FDA Status...
  • Page 141 AURIX™ TC33xEXT Memory Test Unit (MTU) Field Bits Type Description RESz (z=0-1,3- Reserved 7,10,13- Reserved. Not used in this product. 15,18,20- 29,31) CPU0_DMEM1 CPU0 DMEM1 Test FDA Status _FDA SSH MSTATUS.FDA = 0 SSH MSTATUS.FDA = 1 Reserved - Res Reserved.
  • Page 142 AURIX™ TC33xEXT Memory Test Unit (MTU) MTU_MEMFDAi (i=2) Memory Test FDA Status Register i (0060 +i*4) Application Reset Value: 0000 0000 SPU_F SPU_F SPU_F SPU_F HSPD GIGET GIGET SDMM FT30_ FT20_ FT10_ FT00_ M_RA RES31 RES29 RES27 RES25 RES23 RES22 H_TX_ H_RX_ RES17 RES16...
  • Page 143 AURIX™ TC33xEXT Memory Test Unit (MTU) Field Bits Type Description HSPDM_RAM_ HDSPDM RAM Test FDA Status SSH MSTATUS.FDA = 0 SSH MSTATUS.FDA = 1 SPU_FFT00_R SPU FFT00 RAM Test FDA Status AM_FDA SSH MSTATUS.FDA = 0 SSH MSTATUS.FDA = 1 SPU_FFT10_R SPU FFT10 RAM Test FDA Status AM_FDA...

  • Page 144: Ssh Instances

    AURIX™ TC33xEXT Memory Test Unit (MTU) 13.5 SSH Instances The system SRAMs do not all have the same configuration. Table 53 “SSH instances” on Page 22 shows the instance-specific configurations of the SRAM Support Hardware. The ECC values for all SRAMs are computed only out of the data information*. The base address of an SSH instance MCx can be calculated from the MC_BASE (defined in the platform chapter) as: Base Address of SSH instance x (MCx) = MC_BASE + x*0x100 Table 53...
  • Page 145 AURIX™ TC33xEXT Memory Test Unit (MTU) Table 53 SSH instances (cont’d) (MCx) Module Error Addr Buffer ECC type ECC granularity (ETRR) Depth Factor Reserved Reserved Reserved Reserved CPU0_DMEM1 SECDED Reserved 36-37 Reserved Reserved Reserved SADMA SECDED Reserved MCDS EMEM SECDED Reserved Reserved Reserved...
  • Page 146 AURIX™ TC33xEXT Memory Test Unit (MTU) Table 53 SSH instances (cont’d) (MCx) Module Error Addr Buffer ECC type ECC granularity (ETRR) Depth Factor Reserved Reserved Reserved SCR_XRAM SECDED SCR_RAMINT SECDED Reserved Reserved Reserved GIGETH_RX_RAM SECDED GIGETH_TX_RAM SECDED SDMMC SECDED HSPDM SECDED 86- 87 Reserved SPU_FFT0...

  • Page 147: Ganging For Sram Test And Initialization

    AURIX™ TC33xEXT Memory Test Unit (MTU) 13.5.1 Ganging for SRAM test and initialization Whenever an MBIST test or SRAM initialization is started via the MTU/SSH, there is a certain jump in the current consumption, due to the parallel accesses to the SRAM cells during the test or initialization. This current jump is different for the different SRAMs in the product, and depends on the size of the SRAM, the clock frequency e.t.c.

  • Page 148: Connectivity

    AURIX™ TC33xEXT Memory Test Unit (MTU) Table 56 GANG-2 MCx(x=) Module / SRAM CPU0_PMEM CPU0_PTAG CPU0_DLMU_STBY CPU1_DTAG CPU1_PMEM CPU1_PTAG EMEM_XTM SPU_BUFFER0 SPU_FFT00 Table 57 GANG-3 MCx(x=) Module / SRAM CPU0_DTAG SADMA SPU_FFT10 SPU_FFT20 SPU_FFT30 13.6 Connectivity Table 58 Connections of MTU Interface Signals connects Description...

  • Page 149: Revision History

    AURIX™ TC33xEXT Memory Test Unit (MTU) 13.7 Revision History Table 59 Revision History Reference Change to Previous Version Comment V7.4.7 Initial version for TC33X. V7.4.8 Page 27 Revision History entries up to V7.4.7 removed. Page 8 MEMMAP Reserved (not implemented) bits changed to “read”. Settings for bitfield CPU1_DMEM1 corrected in MEMTEST, MEMSTAT, MEMDONE and MEMFDA registers.

  • Page 150: General Purpose I/O Ports And Peripheral I/O Lines (Ports)

    AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) General Purpose I/O Ports and Peripheral I/O Lines (Ports) This chapter supplements the family documentation with device specific information for TC33xEXT. 14.1 TC33xEXT Specific IP Configuration The Ports configuration (which Port modules are implemented, their width and functionality) is represented by the device specific register set shown in this chapter.
  • Page 151 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 61 Register Overview - P00 (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write P00_IOCR8 Port 00 Input/Output U,SV U,SV,P See page Control Register 8 P00_IOCR12...
  • Page 152 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 61 Register Overview - P00 (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write P00_OMSR Port 00 Output Modification U,SV U,SV,P Application Set Register...
  • Page 153 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 62 Register Overview - P02 (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write P02_ESR Port 02 Emergency Stop U,SV SV,E,P Application Register...
  • Page 154 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 63 Register Overview - P10 (ascending Offset Address) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write P10_OUT Port 10 Output Register U,SV U,SV,P Application Reset P10_OMR...
  • Page 155 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 63 Register Overview - P10 (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write P10_OMCR0 Port 10 Output Modification U,SV U,SV,P Application Clear Register 0...
  • Page 156 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 64 Register Overview - P11 (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write Reserved (004 Byte) (x=0-5) P11_PDR0 Port 11 Pad Driver Mode U,SV SV,E,P See page...
  • Page 157 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 64 Register Overview - P11 (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write Reserved (004 Byte) (x=0-13) P11_ACCEN1 Port 11 Access Enable U,SV SV,SE Application...
  • Page 158 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 65 Register Overview - P12 (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write P12_OMCR0 Port 12 Output Modification U,SV U,SV,P Application Clear Register 0...
  • Page 159 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 66 Register Overview - P14 (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write Reserved (004 Byte) (x=0-1) P14_ESR Port 14 Emergency Stop U,SV SV,E,P Application...
  • Page 160 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 67 Register Overview - P15 (ascending Offset Address) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write P15_OUT Port 15 Output Register U,SV U,SV,P Application Reset P15_OMR...
  • Page 161 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 67 Register Overview - P15 (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write P15_OMCR0 Port 15 Output Modification U,SV U,SV,P Application Clear Register 0...
  • Page 162 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 68 Register Overview - P20 (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write Reserved (004 Byte) (x=0-5) P20_PDR0 Port 20 Pad Driver Mode U,SV SV,E,P See page...
  • Page 163 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 68 Register Overview - P20 (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write Reserved (004 Byte) (x=0-13) P20_ACCEN1 Port 20 Access Enable U,SV SV,SE Application...
  • Page 164 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 69 Register Overview - P21 (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write P21_OMSR0 Port 21 Output Modification U,SV U,SV,P Application Set Register 0...
  • Page 165 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 70 Register Overview - P22 (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write Reserved (004 Byte) (x=0-5) P22_PDR0 Port 22 Pad Driver Mode U,SV SV,E,P See page...
  • Page 166 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 71 Register Overview - P23 (ascending Offset Address) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write P23_OUT Port 23 Output Register U,SV U,SV,P Application Reset P23_OMR...
  • Page 167 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 71 Register Overview - P23 (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write P23_OMCR Port 23 Output Modification U,SV U,SV,P Application Clear Register...
  • Page 168 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 72 Register Overview - P32 (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write P32_PCSR Port 32 Pin Controller Select U,SV SV,SE Application...
  • Page 169 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 73 Register Overview - P33 (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write P33_IOCR8 Port 33 Input/Output U,SV U,SV,P See page Control Register 8 P33_IOCR12...
  • Page 170 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 73 Register Overview - P33 (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write P33_OMSR Port 33 Output Modification U,SV U,SV,P Application Set Register...
  • Page 171 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 74 Register Overview - P34 (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write P34_PCSR Port 34 Pin Controller Select U,SV SV,SE Application...

  • Page 172: Pn Registers

    AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) 14.3 Pn Registers 14.3.1 SPB bus slave interface Port 00 Output Register The port output register determines the value of a GPIO pin when it is selected by Pn_IOCRx as output. Writing a 0 to a Pn_OUT.Px (x = 0-15) bit position delivers a low level at the corresponding output pin.
  • Page 173 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 75 Access Mode Restrictions sorted by descending priority Applies to P00_OUT Applies to P11_OUT Applies to P20_OUT Applies to P33_OUT Mode Name Access Mode Description Master enabled in rwh Px (x=0-15) write access for enabled masters ACCEN...
  • Page 174 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 76 Access Mode Restrictions sorted by descending priority Applies to P02_OUT Applies to P10_OUT Applies to P14_OUT Applies to P15_OUT Mode Name Access Mode Description Master enabled in rwh Px (x=0-11) write access for enabled masters ACCEN...
  • Page 175 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) P21_OUT Port 21 Output Register (000 Application Reset Value: 0000 0000 P22_OUT Port 22 Output Register (000 Application Reset Value: 0000 0000 P23_OUT Port 23 Output Register (000 Application Reset Value: 0000 0000 P32_OUT Port 32 Output Register (000...
  • Page 176 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) P00_OMR Port 00 Output Modification Register (004 Application Reset Value: 0000 0000 P11_OMR Port 11 Output Modification Register (004 Application Reset Value: 0000 0000 P20_OMR Port 20 Output Modification Register (004 Application Reset Value: 0000 0000 P33_OMR...
  • Page 177 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 80 Function of the Bits PCLx and PSx PCLx Function Bit Pn_OUT.Px is not changed. Bit Pn_OUT.Px is set. Bit Pn_OUT.Px is reset. Bit Pn_OUT.Px is toggled. P02_OMR Port 02 Output Modification Register (004 Application Reset Value: 0000 0000...
  • Page 178 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 81 Access Mode Restrictions sorted by descending priority Applies to P02_OMR Applies to P10_OMR Applies to P14_OMR Applies to P15_OMR Mode Name Access Mode Description Master enabled in PCLx (x=0-11), PSx (x=0-11) write access for enabled masters ACCEN...
  • Page 179 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 82 Access Mode Restrictions sorted by descending priority Applies to P12_OMR Applies to P34_OMR Mode Name Access Mode Description Master enabled in PCLx (x=0-3), PSx (x=0-3) write access for enabled masters ACCEN Otherwise (default) r0 PCLx (x=0-3), PSx (x=0-3)
  • Page 180 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 83 Access Mode Restrictions sorted by descending priority Applies to P21_OMR Applies to P22_OMR Applies to P23_OMR Applies to P32_OMR Mode Name Access Mode Description Master enabled in PCLx (x=0-7), PSx (x=0-7) write access for enabled masters ACCEN...
  • Page 181 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) Field Bits Type Description MODTYPE 15:8 Module Type This bit field is C0 . It defines a 32-bit module MODNUMBER 31:16 Module Number This bit field defines the module identification number. The value for the Ports module is 00C8 P23_ID Port 23 Identification Register...
  • Page 182 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) The reset values of 1010 1010 and 0000 0000 for Pn_IOCRx registers represents input pull-up and no input pull device (tri-state mode) being activated, respectively. The switching of the intended mode of the device is controlled by HWCFG6.When a cold reset is activated and HWCFG6=1, the port pins except P33.8, P40 and P41 are set to input pull-up mode, P33.8, P40 and P41 are in tri-state mode as long as PORST is activated.If HWCFG6=0, the pins have the default state of tri-state mode.
  • Page 183 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) Field Bits Type Description 26:24, Reserved 18:16, 10:8, Read as 0; should be written with 0. Table 84 Access Mode Restrictions sorted by descending priority Applies to P00_IOCR0 Applies to P02_IOCR0 Applies to P10_IOCR0...
  • Page 184 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 86 PCx Coding PCx[4:0] Characteristics Selected Pull-up / Pull-down / Selected Output Function 0XX00 Input – No input pull device connected, tri-state mode 0XX01 Input pull-down device connected 0XX10 Input pull-up device connected 0XX11...
  • Page 185 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) Field Bits Type Description PCx (x=0-3) 8*x+7:8*x+ Port Control for Pin x This bit field defines the Port n line x functionality according to Table 26:24, Reserved 18:16, 10:8, Read as 0;...
  • Page 186 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) P00_IOCR4 Port 00 Input/Output Control Register 4 (014 Reset Value: Table 90 P02_IOCR4 Port 02 Input/Output Control Register 4 (014 Reset Value: Table 90 P10_IOCR4 Port 10 Input/Output Control Register 4 (014 Reset Value: Table 90...
  • Page 187 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 89 Access Mode Restrictions sorted by descending priority Applies to P00_IOCR4 Applies to P02_IOCR4 Applies to P10_IOCR4 Applies to P11_IOCR4 Applies to P14_IOCR4 Applies to P15_IOCR4 Applies to P20_IOCR4 Applies to P21_IOCR4...
  • Page 188 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) Field Bits Type Description PCx (x=4-7) 8*x-25:8*x- Port Control for Port 32 Pin x This bit field defines the Port n line x functionality according to Table 26:24, Reserved 18:16, 10:8, Read as 0;...
  • Page 189 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) P00_IOCR8 Port 00 Input/Output Control Register 8 (018 Reset Value: Table 94 P02_IOCR8 Port 02 Input/Output Control Register 8 (018 Reset Value: Table 94 P10_IOCR8 Port 10 Input/Output Control Register 8 (018 Reset Value: Table 94...
  • Page 190 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 94 Reset Values variant 1 Applies to P00_IOCR8 Applies to P02_IOCR8 Applies to P10_IOCR8 Applies to P11_IOCR8 Applies to P14_IOCR8 Applies to P15_IOCR8 Applies to P20_IOCR8 Reset Type Reset Value Note Application Reset...
  • Page 191 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 96 Access Mode Restrictions sorted by descending priority Applies to P00_IOCR12 Applies to P11_IOCR12 Applies to P20_IOCR12 Applies to P33_IOCR12 Mode Name Access Mode Description Master enabled in PCx (x=12-15) write access for enabled masters ACCEN...
  • Page 192 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) Field Bits Type Description Px (x=0-15) Input Bit x This bit indicates the level at the input pin Pn.x. The input level of Pn.x is 0. The input level of Pn.x is 1. 31:16 Reserved Read as 0.
  • Page 193 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) P12_IN Port 12 Input Register (024 Application Reset Value: 0000 000X P34_IN Port 34 Input Register (024 Application Reset Value: 0000 000X Field Bits Type Description Px (x=0-3) Input Bit x This bit indicates the level at the input pin Pn.x.
  • Page 194 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) Field Bits Type Description 15, 14, 13, Reserved 12, 11, 10, 9, Read as 0; should be written with 0. 31:16 Port 00 Pad Driver Mode Register 0 P00_PDR0 Port 00 Pad Driver Mode Register 0 (040 Reset Value:...
  • Page 195 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 98 Access Mode Restrictions sorted by descending priority Applies to P00_PDR0 Applies to P02_PDR0 Applies to P10_PDR0 Applies to P11_PDR0 Applies to P14_PDR0 Applies to P15_PDR0 Applies to P20_PDR0 Applies to P21_PDR0...
  • Page 196 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 101 Pad Driver Mode Selection for Fast Pads PDx.1 PDx.0 Speed Grade Driver Setting Strong driver, sharp edge (“ss”) Strong driver, medium edge (“sm”) Medium driver (“m”) TC39x A-Step: Medium driver (“m”) Else: Reserved when operating as output.
  • Page 197 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) The boot software configures the reset value of Pn_PDR0 and Pn_PDR1 registers from 0000 0000 to 2222 2222 except for analog ports and if the package doesn’t make any of the related pins available. The resulting value depends on the implemented port width.
  • Page 198 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) P12_PDR0 Port 12 Pad Driver Mode Register 0 (040 Reset Value: Table 107 P34_PDR0 Port 34 Pad Driver Mode Register 0 (040 Reset Value: Table 107 Field Bits Type Description PDx (x=0-3) 4*x+1:4*x...
  • Page 199 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) Port 00 Pad Driver Mode Register 1 P00_PDR1 Port 00 Pad Driver Mode Register 1 (044 Reset Value: Table 109 P11_PDR1 Port 11 Pad Driver Mode Register 1 (044 Reset Value: Table 109 P20_PDR1...
  • Page 200 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) P02_PDR1 Port 02 Pad Driver Mode Register 1 (044 Reset Value: Table 111 P10_PDR1 Port 10 Pad Driver Mode Register 1 (044 Reset Value: Table 111 P14_PDR1 Port 14 Pad Driver Mode Register 1 (044 Reset Value: Table 111...
  • Page 201 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 111 Reset Values Applies to P02_PDR1 Applies to P10_PDR1 Applies to P14_PDR1 Applies to P15_PDR1 Reset Type Reset Value Note After SSW execution 0000 2222 Initial value in largest package After SSW execution 0000 ––––...
  • Page 202 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 112 Access Mode Restrictions sorted by descending priority Applies to P00_ESR Applies to P11_ESR Applies to P20_ESR Mode Name Access Mode Description Master enabled in ENx (x=0-15) write access for enabled masters ACCEN and Supervisor Mode and ENDINIT...
  • Page 203 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) P02_ESR Port 02 Emergency Stop Register (050 Application Reset Value: 0000 0000 P10_ESR Port 10 Emergency Stop Register (050 Application Reset Value: 0000 0000 P14_ESR Port 14 Emergency Stop Register (050 Application Reset Value: 0000 0000 P15_ESR...
  • Page 204 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) P12_ESR Port 12 Emergency Stop Register (050 Application Reset Value: 0000 0000 P34_ESR Port 34 Emergency Stop Register (050 Application Reset Value: 0000 0000 Field Bits Type Description ENx (x=0-3) Emergency Stop Enable for Pin x This bit enables the emergency stop function for all GPIO lines.
  • Page 205 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) P21_ESR Port 21 Emergency Stop Register (050 Application Reset Value: 0000 0000 Field Bits Type Description ENx (x=0-1,3- Emergency Stop Enable for Pin x This bit enables the emergency stop function for all GPIO lines. If the emergency stop condition is met and enabled, the output selection is automatically switched from alternate output function to GPIO input function.
  • Page 206 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) P22_ESR Port 22 Emergency Stop Register (050 Application Reset Value: 0000 0000 P23_ESR Port 23 Emergency Stop Register (050 Application Reset Value: 0000 0000 P32_ESR Port 32 Emergency Stop Register (050 Application Reset Value: 0000 0000 Field...
  • Page 207 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) P33_ESR Port 33 Emergency Stop Register (050 Application Reset Value: 0000 0000 EN15 EN14 EN13 EN12 EN11 EN10 Field Bits Type Description ENx (x=0-7,9- Emergency Stop Enable for Pin x This bit enables the emergency stop function for all GPIO lines.
  • Page 208 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) P00_PDISC Port 00 Pin Function Decision Control Register (060 Reset Value: Table 119 P11_PDISC Port 11 Pin Function Decision Control Register (060 Reset Value: Table 119 P20_PDISC Port 20 Pin Function Decision Control Register (060 Reset Value: Table 119 P33_PDISC...
  • Page 209 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 119 Reset Values Applies to P00_PDISC Applies to P11_PDISC Applies to P20_PDISC Applies to P33_PDISC Reset Type Reset Value Note After SSW execution 0000 0000 Initial value in largest package After SSW execution 0000 ––––...
  • Page 210 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 120 Access Mode Restrictions sorted by descending priority Applies to P02_PDISC Applies to P10_PDISC Applies to P14_PDISC Applies to P15_PDISC Mode Name Access Mode Description Master enabled in PDISx (x=0-11) write access for enabled masters ACCEN and...
  • Page 211 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) Field Bits Type Description 15, 14, 13, Reserved 12, 11, 10, 9, Read as 0; should be written with 0. 8, 7, 6, 5, 4, 31:16 Table 122 Access Mode Restrictions sorted by descending priority Applies to P12_PDISC Applies to...
  • Page 212 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) Field Bits Type Description PDISx (x=0-7) x Pin Function Decision Control for Pin x This bit selects the function of the port pad. Digital functionality of pad Pn.x is enabled. Digital functionality (including pull resistors) of pad Pn.x is disabled.
  • Page 213 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) P00_PCSR Port 00 Pin Controller Select Register (064 Application Reset Value: 0000 0000 P20_PCSR Port 20 Pin Controller Select Register (064 Application Reset Value: 0000 0000 Field Bits Type Description Rx (x=0-15) Reserved...
  • Page 214 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) Field Bits Type Description Rx (x=0-11) Reserved Read as 0; should be written with 0. 15, 14, 13, Reserved Read as 0; should be written with 0. 30:16, Table 127 Access Mode Restrictions sorted by descending priority Applies to P02_PCSR Applies to...
  • Page 215 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 128 Access Mode Restrictions of P11_PCSR sorted by descending priority Mode Name Access Mode Description Supervisor Mode Rx (x=5,7-15) write access only for masters with supervisor mode and Safety ENDINIT SELx (x=0-4,6) Otherwise (default) r Rx (x=5,7-15), SELx (x=0-4,6)
  • Page 216 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) P21_PCSR Port 21 Pin Controller Select Register (064 Application Reset Value: 0000 0000 P22_PCSR Port 22 Pin Controller Select Register (064 Application Reset Value: 0000 0000 P23_PCSR Port 23 Pin Controller Select Register (064 Application Reset Value: 0000 0000 P32_PCSR...
  • Page 217 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) P33_PCSR Port 33 Pin Controller Select Register (064 Application Reset Value: 0000 0100 SEL15 SEL14 SEL13 SEL12 SEL11 SEL10 SEL9 SEL8 SEL7 SEL6 SEL5 SEL4 SEL3 SEL2 SEL1 SEL0 Field Bits Type...
  • Page 218 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) P34_PCSR Port 34 Pin Controller Select Register (064 Application Reset Value: 0000 0000 SEL1 Field Bits Type Description SELx (x=1) Output Select for Pin x This bit enables or disables SCR control. Tricore selected for data and control of pin x and not SCR.
  • Page 219 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) Register Pn_OMSR0 sets the logic state of Pn.[3:0] port lines P00_OMSR0 Port 00 Output Modification Set Register 0 (070 Application Reset Value: 0000 0000 P02_OMSR0 Port 02 Output Modification Set Register 0 (070 Application Reset Value: 0000 0000 P10_OMSR0...
  • Page 220 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 133 Access Mode Restrictions sorted by descending priority Applies to P00_OMSR0 Applies to P02_OMSR0 Applies to P10_OMSR0 Applies to P11_OMSR0 Applies to P12_OMSR0 Applies to P14_OMSR0 Applies to P15_OMSR0 Applies to P20_OMSR0...
  • Page 221 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 134 Access Mode Restrictions sorted by descending priority Applies to P23_OMSR0 Applies to P32_OMSR0 Applies to P33_OMSR0 Applies to P34_OMSR0 Mode Name Access Mode Description Master enabled in PSx (x=0-3) write access for enabled masters ACCEN...
  • Page 222 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) Field Bits Type Description PSx (x=4-7) Set Bit x Setting this bit will set the corresponding bit in the port output register Pn_OUT. Read as 0. No operation Sets Pn_OUT.Px 3:0, Reserved 31:8...
  • Page 223 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) Field Bits Type Description 3:0, Reserved 31:8 Read as 0; should be written with 0. Table 136 Access Mode Restrictions sorted by descending priority Applies to P32_OMSR4 Applies to P33_OMSR4 Mode Name Access Mode...
  • Page 224 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) Field Bits Type Description 7:0, Reserved 31:12 Read as 0; should be written with 0. Table 137 Access Mode Restrictions sorted by descending priority Applies to P00_OMSR8 Applies to P02_OMSR8 Applies to P10_OMSR8...
  • Page 225 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 138 Access Mode Restrictions sorted by descending priority Applies to P00_OMSR12 Applies to P11_OMSR12 Applies to P20_OMSR12 Applies to P33_OMSR12 Mode Name Access Mode Description Master enabled in PSx (x=12-15) write access for enabled masters ACCEN...
  • Page 226 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) Field Bits Type Description PCLx (x=0-3) x+16 Clear Bit x Setting this bit will clear the corresponding bit in the port output register Pn_OUT. Read as 0. No operation Clears Pn_OUT.Px 15:0, Reserved...
  • Page 227 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) Field Bits Type Description PCLx (x=0-3) x+16 Clear Bit x Setting this bit will clear the corresponding bit in the port output register Pn_OUT. Read as 0. No operation Clears Pn_OUT.Px 15:0, Reserved...
  • Page 228 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) P00_OMCR4 Port 00 Output Modification Clear Register 4 (084 Application Reset Value: 0000 0000 P02_OMCR4 Port 02 Output Modification Clear Register 4 (084 Application Reset Value: 0000 0000 P10_OMCR4 Port 10 Output Modification Clear Register 4 (084 Application Reset Value: 0000 0000...
  • Page 229 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 141 Access Mode Restrictions sorted by descending priority Applies to P00_OMCR4 Applies to P02_OMCR4 Applies to P10_OMCR4 Applies to P11_OMCR4 Applies to P14_OMCR4 Applies to P15_OMCR4 Applies to P20_OMCR4 Applies to P21_OMCR4...
  • Page 230 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 142 Access Mode Restrictions sorted by descending priority Applies to P32_OMCR4 Applies to P33_OMCR4 Mode Name Access Mode Description Master enabled in PCLx (x=4-7) write access for enabled masters ACCEN Otherwise (default) r0 PCLx (x=4-7)
  • Page 231 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 143 Access Mode Restrictions sorted by descending priority Applies to P00_OMCR8 Applies to P02_OMCR8 Applies to P10_OMCR8 Applies to P11_OMCR8 Applies to P14_OMCR8 Applies to P15_OMCR8 Applies to P20_OMCR8 Applies to P33_OMCR8...
  • Page 232 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 144 Access Mode Restrictions sorted by descending priority Applies to P00_OMCR12 Applies to P11_OMCR12 Applies to P20_OMCR12 Applies to P33_OMCR12 Mode Name Access Mode Description Master enabled in PCLx (x=12-15) write access for enabled masters ACCEN...
  • Page 233 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 145 Access Mode Restrictions sorted by descending priority Applies to P00_OMSR Applies to P11_OMSR Applies to P20_OMSR Applies to P33_OMSR Mode Name Access Mode Description Master enabled in PSx (x=0-15) write access for enabled masters ACCEN...
  • Page 234 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 146 Access Mode Restrictions sorted by descending priority Applies to P02_OMSR Applies to P10_OMSR Applies to P14_OMSR Applies to P15_OMSR Mode Name Access Mode Description Master enabled in PSx (x=0-11) write access for enabled masters ACCEN...
  • Page 235 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) P21_OMSR Port 21 Output Modification Set Register (090 Application Reset Value: 0000 0000 P22_OMSR Port 22 Output Modification Set Register (090 Application Reset Value: 0000 0000 P23_OMSR Port 23 Output Modification Set Register (090 Application Reset Value: 0000 0000 P32_OMSR...
  • Page 236 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) P00_OMCR Port 00 Output Modification Clear Register (094 Application Reset Value: 0000 0000 P11_OMCR Port 11 Output Modification Clear Register (094 Application Reset Value: 0000 0000 P20_OMCR Port 20 Output Modification Clear Register (094 Application Reset Value: 0000 0000 P33_OMCR...
  • Page 237 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) P02_OMCR Port 02 Output Modification Clear Register (094 Application Reset Value: 0000 0000 P10_OMCR Port 10 Output Modification Clear Register (094 Application Reset Value: 0000 0000 P14_OMCR Port 14 Output Modification Clear Register (094 Application Reset Value: 0000 0000 P15_OMCR...
  • Page 238 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) P12_OMCR Port 12 Output Modification Clear Register (094 Application Reset Value: 0000 0000 P34_OMCR Port 34 Output Modification Clear Register (094 Application Reset Value: 0000 0000 PCL3 PCL2 PCL1 PCL0 Field Bits Type...
  • Page 239 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) P21_OMCR Port 21 Output Modification Clear Register (094 Application Reset Value: 0000 0000 P22_OMCR Port 22 Output Modification Clear Register (094 Application Reset Value: 0000 0000 P23_OMCR Port 23 Output Modification Clear Register (094 Application Reset Value: 0000 0000 P32_OMCR...
  • Page 240 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) Attention: The bit field P21_LPCR2.PS configures the pad supply for the LVDS bias distributor for all (not-RIF) LVDS pads and for the oscillator. Therefore even if no LVDS pad is used, this field has to be configured to the correct pad supply level.
  • Page 241 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 154 Reset Values of P21_LPCRx (x=2) Reset Type Reset Value Note After SSW execution 0000 0080 Initial value of RX depends on trimming Port 00 Access Enable Register 1 Each port has its own dedicated ACCEN0 and ACCEN1 registers.
  • Page 242 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 155 Access Mode Restrictions sorted by descending priority Applies to P00_ACCEN1 Applies to P02_ACCEN1 Applies to P10_ACCEN1 Applies to P11_ACCEN1 Applies to P12_ACCEN1 Applies to P14_ACCEN1 Applies to P15_ACCEN1 Applies to P20_ACCEN1...
  • Page 243 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 156 Access Mode Restrictions sorted by descending priority Applies to P23_ACCEN1 Applies to P32_ACCEN1 Applies to P33_ACCEN1 Applies to P34_ACCEN1 Mode Name Access Mode Description Supervisor Mode See bit field definitions above write access only for masters with supervisor mode and Safety ENDINIT Otherwise (default) -...
  • Page 244 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) P00_ACCEN0 Port 00 Access Enable Register 0 (0FC Application Reset Value: FFFF FFFF P02_ACCEN0 Port 02 Access Enable Register 0 (0FC Application Reset Value: FFFF FFFF P10_ACCEN0 Port 10 Access Enable Register 0 (0FC Application Reset Value: FFFF FFFF P11_ACCEN0...
  • Page 245 AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 157 Access Mode Restrictions sorted by descending priority Applies to P00_ACCEN0 Applies to P02_ACCEN0 Applies to P10_ACCEN0 Applies to P11_ACCEN0 Applies to P12_ACCEN0 Applies to P14_ACCEN0 Applies to P15_ACCEN0 Applies to P20_ACCEN0...

  • Page 246: Device Specific Connectivity Documentation

    AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 158 Access Mode Restrictions sorted by descending priority Applies to P23_ACCEN0 Applies to P32_ACCEN0 Applies to P33_ACCEN0 Applies to P34_ACCEN0 Mode Name Access Mode Description Supervisor Mode ENx (x=0-31) write access only for masters with supervisor mode and Safety ENDINIT Otherwise (default) r...

  • Page 247: Revision History

    AURIX™ TC33xEXT General Purpose I/O Ports and Peripheral I/O Lines (Ports) 14.5 Revision History Table 159 Revision History Reference Changes to Previous Version Comment V1.8.20 – This is the first version for TC33xEXT. – V1.8.21 – No content of this Appx changed. TC3Ax Appx added to delivery package and change in Feature List of family chapter.

  • Page 248: Safety Management Unit (Smu)

    AURIX™ TC33xEXT Safety Management Unit (SMU) Safety Management Unit (SMU) This chapter describes the Safety Management Unit (short SMU) module of the TC33xEXT. 15.1 TC33xEXT Specific IP Configuration See features in family spec. User’s Manual 15-1 V2.0.0 SMUV4.0.23 2021-02 OPEN MARKET VERSION...

  • Page 249: Tc33Xext Specific Register Set

    AURIX™ TC33xEXT Safety Management Unit (SMU) 15.2 TC33xEXT Specific Register Set SMU_core Specific Register Set Register Address Space Table Table 160 Register Address Space - SMU Module Base Address End Address Note F0036800 F0036FFF FPI slave interface Register Overview Table Table 161 Register Overview - SMU (ascending Offset Address) Short Name Long Name...
  • Page 250 AURIX™ TC33xEXT Safety Management Unit (SMU) Table 161 Register Overview - SMU (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write SMU_PCTL Port Control U,SV SV,P,SE,32 PowerOn Reset Family Spec SMU_AFCNT Alarm and Fault Counter U,SV PowerOn Reset Family...

  • Page 251: Tc33Xext Specific Registers

    AURIX™ TC33xEXT Safety Management Unit (SMU) Table 161 Register Overview - SMU (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write SMU_RMEF Register Monitor Error Flags 304 U,SV SV,P,SE,32 Application Reset Family Spec SMU_RMSTS Register Monitor Self Test...

  • Page 252: Tc33Xext Specific Registers

    AURIX™ TC33xEXT Safety Management Unit (SMU) 15.3.1 TC33xEXT Specific Registers 15.3.1.1 FPI slave interface Alarm Configuration Register SMU_AGiCFj (i=0-1;j=0-2) Alarm Configuration Register (100 +i*12+j*4) Application Reset Value: 0000 0000 CF24 CF23 CF22 CF14 CF13 CF12 CF11 CF10 Field Bits Type Description CFz (z=0-2,4- Configuration flag x (x=0-2) for alarm z belonging to alarm group i.
  • Page 253 AURIX™ TC33xEXT Safety Management Unit (SMU) Field Bits Type Description 31, 30, 29, Reserved 28, 27, 26, Read as 0; should be written with 0. 25, 24, 23, 22, 21, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, SMU_AGiCFj (i=6;j=0-2)
  • Page 254 AURIX™ TC33xEXT Safety Management Unit (SMU) SMU_AGiCFj (i=7;j=0-2) Alarm Configuration Register (100 +i*12+j*4) Application Reset Value: 0000 0000 CF31 CF30 CF29 CF28 CF27 CF26 CF25 CF24 CF23 CF22 CF21 CF20 CF17 CF16 CF15 CF14 CF13 CF12 Field Bits Type Description CFz (z=0-8,12- Configuration flag x (x=0-2) for alarm z belonging to alarm group i.
  • Page 255 AURIX™ TC33xEXT Safety Management Unit (SMU) SMU_AGiCFj (i=9;j=0-2) Alarm Configuration Register (100 +i*12+j*4) Application Reset Value: 0000 0000 CF30 CF28 CF22 CF21 CF20 CF17 CF16 CF15 Field Bits Type Description CFz (z=0- Configuration flag x (x=0-2) for alarm z belonging to alarm group i. 1,3,5,15- The configuration flags 0, 1 and 2 must be used together to define the 17,20-...
  • Page 256 AURIX™ TC33xEXT Safety Management Unit (SMU) Field Bits Type Description 31, 30, 29, Reserved 28, 27, 26, Read as 0; should be written with 0. 25, 24, 23, SMU_AGiCFj (i=11;j=0-2) Alarm Configuration Register (100 +i*12+j*4) Application Reset Value: 0000 0000 CF13 CF12 Field Bits...
  • Page 257 AURIX™ TC33xEXT Safety Management Unit (SMU) Field Bits Type Description FEz (z=0-2,4- Fault signaling configuration flag for alarm z belonging to alarm 14,22-24) group i. FSP disabled for this alarm event FSP enabled for this alarm event 31, 30, 29, Reserved 28, 27, 26, Read as 0;...
  • Page 258 AURIX™ TC33xEXT Safety Management Unit (SMU) Field Bits Type Description FEz (z=0-8,16- Fault signaling configuration flag for alarm z belonging to alarm 21,23-25) group i. FSP disabled for this alarm event FSP enabled for this alarm event 31, 30, 29, Reserved 28, 27, 26, Read as 0;...
  • Page 259 AURIX™ TC33xEXT Safety Management Unit (SMU) Field Bits Type Description FEz (z=0- Fault signaling configuration flag for alarm z belonging to alarm 11,16-23,25- group i. FSP disabled for this alarm event FSP enabled for this alarm event 24, 15, 14, Reserved 13, 12 Read as 0;...
  • Page 260 AURIX™ TC33xEXT Safety Management Unit (SMU) Field Bits Type Description FEz (z=0- Fault signaling configuration flag for alarm z belonging to alarm 18,20-22) group i. FSP disabled for this alarm event FSP enabled for this alarm event 31, 30, 29, Reserved 28, 27, 26, Read as 0;...
  • Page 261 AURIX™ TC33xEXT Safety Management Unit (SMU) SMU_AGi (i=0-1) Alarm Status Register (1C0 +i*4) Application Reset Value: 0000 0000 SF24 SF23 SF22 SF14 SF13 SF12 SF11 SF10 Field Bits Type Description SFz (z=0-2,4- Status flag for alarm z belonging to alarm group i. 14,22-24) Status flag z does not report a fault condition Status flag z reports a fault condition...
  • Page 262 AURIX™ TC33xEXT Safety Management Unit (SMU) SMU_AGi (i=6) Alarm Status Register (1C0 +i*4) Application Reset Value: 0000 0000 SF25 SF24 SF23 SF21 SF20 SF19 SF18 SF17 SF16 Field Bits Type Description SFz (z=0-8,16- Status flag for alarm z belonging to alarm group i. 21,23-25) Status flag z does not report a fault condition Status flag z reports a fault condition...
  • Page 263 AURIX™ TC33xEXT Safety Management Unit (SMU) SMU_AGi (i=8) Alarm Status Register (1C0 +i*4) Application Reset Value: 0000 0000 SF31 SF30 SF29 SF28 SF27 SF26 SF25 SF23 SF22 SF21 SF20 SF19 SF18 SF17 SF16 SF11 SF10 Field Bits Type Description SFz (z=0- Status flag for alarm z belonging to alarm group i.
  • Page 264 AURIX™ TC33xEXT Safety Management Unit (SMU) SMU_AGi (i=10) Alarm Status Register (1C0 +i*4) Application Reset Value: 0000 0000 SF22 SF21 SF20 SF18 SF17 SF16 SF15 SF14 SF13 SF12 SF11 SF10 Field Bits Type Description SFz (z=0- Status flag for alarm z belonging to alarm group i. 18,20-22) Status flag z does not report a fault condition Status flag z reports a fault condition...
  • Page 265 AURIX™ TC33xEXT Safety Management Unit (SMU) SMU_ADi (i=0-1) Alarm Debug Register (200 +i*4) PowerOn Reset Value: 0000 0000 DF24 DF23 DF22 DF14 DF13 DF12 DF11 DF10 Field Bits Type Description DFz (z=0-2,4- Diagnosis flag for alarm z belonging to alarm group i. 14,22-24) The diagnosis registers make a snapshot of the alarm group status registers when either the executed alarm action is a reset or a state...
  • Page 266 AURIX™ TC33xEXT Safety Management Unit (SMU) SMU_ADi (i=6) Alarm Debug Register (200 +i*4) PowerOn Reset Value: 0000 0000 DF25 DF24 DF23 DF21 DF20 DF19 DF18 DF17 DF16 Field Bits Type Description DFz (z=0-8,16- Diagnosis flag for alarm z belonging to alarm group i. 21,23-25) The diagnosis registers make a snapshot of the alarm group status registers when either the executed alarm action is a reset or a state...
  • Page 267 AURIX™ TC33xEXT Safety Management Unit (SMU) SMU_ADi (i=8) Alarm Debug Register (200 +i*4) PowerOn Reset Value: 0000 0000 DF31 DF30 DF29 DF28 DF27 DF26 DF25 DF23 DF22 DF21 DF20 DF19 DF18 DF17 DF16 DF11 DF10 Field Bits Type Description DFz (z=0- Diagnosis flag for alarm z belonging to alarm group i.
  • Page 268 AURIX™ TC33xEXT Safety Management Unit (SMU) SMU_ADi (i=10) Alarm Debug Register (200 +i*4) PowerOn Reset Value: 0000 0000 DF22 DF21 DF20 DF18 DF17 DF16 DF15 DF14 DF13 DF12 DF11 DF10 Field Bits Type Description DFz (z=0- Diagnosis flag for alarm z belonging to alarm group i. 18,20-22) The diagnosis registers make a snapshot of the alarm group status registers when either the executed alarm action is a reset or a state...

  • Page 269: Tc33Xext Specific Alarm Mapping

    AURIX™ TC33xEXT Safety Management Unit (SMU) Field Bits Type Description 31, 30, 29, Reserved 28, 27, 26, Read as 0; should be written with 0. 25, 24, 23, 22, 21, 20, 19, 18, 17, 16, 15, 14, 11, 10, 8 15.4 TC33xEXT Specific Alarm Mapping This section defines the mapping between the alarm signals at the input of the SMU in the TC33xEXT and the...
  • Page 270 AURIX™ TC33xEXT Safety Management Unit (SMU) Table 162 MTU Pre-Alarm Mapping (cont’d) Alarm Source Logic Alarm Index DMA - Uncorrectable Critical error ALM6[20] MCDS - Uncorrectable Critical error SCR.XRAM - Uncorrectable critical error SCR.RAMINT - Uncorrectable Critical error GIGETHERNET.RX0 - Uncorrectable Critical error GIGETHERNET.TX0 - Uncorrectable Critical error SDMMC - Uncorrectable Critical error DMA - Miscellaneous error...
  • Page 271 AURIX™ TC33xEXT Safety Management Unit (SMU) Safety Flip-flop Pre-Alarm Mapping Table 163 Safety Flip-flop Pre-Alarm Mapping Alarm Source Logic Alarm Index MTU - Safety flip-flop uncorrectable error ALM10[21] IOM - Safety flip-flop uncorrectable error EMEM - Safety flip-flop uncorrectable error IR - Safety flip-flop uncorrectable error SCU - Safety flip-flop uncorrectable error PMS - Safety flip-flop uncorrectable error...

  • Page 272: Tc33Xext Specific Alarms

    AURIX™ TC33xEXT Safety Management Unit (SMU) Table 166 PMS Pre-Alarm Mapping (cont’d) Alarm Source Logic Alarm Index PMS.VDD - Over voltage ALM9[3] PMS.VDDPD - Over voltage PMS.VDDP3 - Over voltage PMS.VDDM - Over voltage PMS.VEXT - Over voltage PMS.VEVRSB - Over voltage PMS.VDD - Under voltage ALM9[5] PMS.VDDPD - Under voltage...
  • Page 273 AURIX™ TC33xEXT Safety Management Unit (SMU) Alarm Mapping related to ALM0 group Table 167 Alarm Mapping related to ALM0 group Alarm Index Module Safety Mechanism & Alarm Indication ALM0[0] cpu_pfi_pfrwb_0 Safety Mechanism: Lockstep CPU Alarm: CPU0 Lockstep Comparator Error Alarm Type: Pulse Note: For non-Lockstep CPUs (CPUs where no lockstep is implemented or where the lockstep is disabled by the user), this alarm only covers faults that might happen on the access path to the...
  • Page 274 AURIX™ TC33xEXT Safety Management Unit (SMU) Table 167 Alarm Mapping related to ALM0 group (cont’d) Alarm Index Module Safety Mechanism & Alarm Indication ALM0[12] Safety Mechanism: SRAM Monitor Alarm: CPU0 DCACHE TAG Single bit error correction Alarm Type: Level ALM0[13] Safety Mechanism: SRAM Monitor Alarm: CPU0 DCACHE TAG Uncorrectable critical error detection Alarm Type: Level...
  • Page 275 AURIX™ TC33xEXT Safety Management Unit (SMU) Table 168 Alarm Mapping related to ALM1 group (cont’d) Alarm Index Module Safety Mechanism & Alarm Indication ALM1[2] cpu_1 Safety Mechanism: PFLASH Read Path Monitor Alarm: CPU1 PFLASH1 Read Path Error Alarm Type: Pulse Note: If the CPU side PFLASH bank does not exist, PFLASH read path lockstep still exist.
  • Page 276 AURIX™ TC33xEXT Safety Management Unit (SMU) Table 168 Alarm Mapping related to ALM1 group (cont’d) Alarm Index Module Safety Mechanism & Alarm Indication ALM1[22] cpu_1 Safety Mechanism: SRI End-to-End EDC Alarm: CPU1 Instruction Fetch SRI Interface EDC Error Alarm Type: Pulse ALM1[23] cpu_1 Safety Mechanism: SRI End-to-End EDC...
  • Page 277 AURIX™ TC33xEXT Safety Management Unit (SMU) Alarm Mapping related to ALM4 group Table 171 Alarm Mapping related to ALM4 group Alarm Index Module Safety Mechanism & Alarm Indication ALM4[2:0] Reserved Reserved ALM4[3] Reserved Reserved ALM4[14:4] Reserved Reserved ALM4[21:15] Reserved Reserved ALM4[24:22] Reserved Reserved...
  • Page 278 AURIX™ TC33xEXT Safety Management Unit (SMU) Table 173 Alarm Mapping related to ALM6 group (cont’d) Alarm Index Module Safety Mechanism & Alarm Indication ALM6[6] Safety Mechanism: Safety Flip-flop Alarm: Safety flip-flop uncorrectable error detected Alarm Type: Level ALM6[7] SMU_CORE Safety Mechanism: Safety Flip-flop Alarm: Safety flip-flop uncorrectable error detected Alarm Type: Level ALM6[8]...
  • Page 279 AURIX™ TC33xEXT Safety Management Unit (SMU) Alarm Mapping related to ALM7 group Table 174 Alarm Mapping related to ALM7 group Alarm Index Module Safety Mechanism & Alarm Indication ALM7[0] Safety Mechanism: SRAM Monitor Alarm: LMU/FSI_RAM Single bit error correction Alarm Type: Level ALM7[1] Safety Mechanism: SRAM Monitor Alarm: LMU/FSI_RAM Uncorrectable critical error detection...
  • Page 280 AURIX™ TC33xEXT Safety Management Unit (SMU) Table 174 Alarm Mapping related to ALM7 group (cont’d) Alarm Index Module Safety Mechanism & Alarm Indication ALM7[16] EMEMWRAPPER Safety Mechanism: LMU Error Detection Code (EDC) Alarm: EDC Read Phase Error Alarm Type: Pulse ALM7[17] Safety Mechanism: Built-in SRI Error Detection Alarm: XBAR0 Bus Error Event...
  • Page 281 AURIX™ TC33xEXT Safety Management Unit (SMU) Table 174 Alarm Mapping related to ALM7 group (cont’d) Alarm Index Module Safety Mechanism & Alarm Indication ALM7[30] Safety Mechanism: PFlash Configuration Monitor Alarm: CPU FLASHCON Configuration Error Alarm Type: Level ALM7[31] Safety Mechanism: PFlash Configuration Monitor Alarm: Flash Stored Configuration Error Alarm Type: Level Alarm Mapping related to ALM8 group...
  • Page 282 AURIX™ TC33xEXT Safety Management Unit (SMU) Table 175 Alarm Mapping related to ALM8 group (cont’d) Alarm Index Module Safety Mechanism & Alarm Indication ALM8[11] Safety Mechanism: Watchdog Alarm: CPU1 Watchdog Time-out Alarm Type: Pulse ALM8[12] Reserved Reserved ALM8[13] Reserved Reserved ALM8[15:14] Reserved Reserved...
  • Page 283 AURIX™ TC33xEXT Safety Management Unit (SMU) Table 175 Alarm Mapping related to ALM8 group (cont’d) Alarm Index Module Safety Mechanism & Alarm Indication ALM8[27] Safety Mechanism: External Alarm Alarm: External Request Unit Alarm 5 Alarm Type: Pulse ALM8[28] Safety Mechanism: External Alarm Alarm: External Request Unit Alarm 6 Alarm Type: Pulse ALM8[29]...
  • Page 284 AURIX™ TC33xEXT Safety Management Unit (SMU) Table 176 Alarm Mapping related to ALM9 group (cont’d) Alarm Index Module Safety Mechanism & Alarm Indication ALM9[17] Page 24 Safety Mechanism: Voltage Monitor Alarm: Under-voltage Alarm Alarm Type: Level ALM9[19:18] Reserved Reserved ALM9[20] EMEMWRAPPER Safety Mechanism: EMEM Monitor Alarm: Unexpected Write to EMEM Alarm...
  • Page 285 AURIX™ TC33xEXT Safety Management Unit (SMU) Table 177 Alarm Mapping related to ALM10 group (cont’d) Alarm Index Module Safety Mechanism & Alarm Indication ALM10[4] Software Safety Mechanism: Software Monitor Alarm: Software Alarm 4 Alarm Type: Pulse ALM10[5] Software Safety Mechanism: Software Monitor Alarm: Software Alarm 5 Alarm Type: Pulse ALM10[6]...
  • Page 286 AURIX™ TC33xEXT Safety Management Unit (SMU) Table 177 Alarm Mapping related to ALM10 group (cont’d) Alarm Index Module Safety Mechanism & Alarm Indication ALM10[18] Safety Mechanism: ErrorPin Alarm: ErrorPin Fault State Activation Alarm Type: Pulse ALM10[19] Reserved Reserved ALM10[20] Safety Mechanism: Safety Flip-flop Alarm: Safety flip-flop correctable error detected Alarm Type: Level ALM10[21]...
  • Page 287 AURIX™ TC33xEXT Safety Management Unit (SMU) Table 178 Alarm Mapping related to ALM11 group (cont’d) Alarm Index Module Safety Mechanism & Alarm Indication ALM11[8] Reserved Reserved ALM11[9] SFIBRIDGE1 Safety Mechanism: SRI Error Detection Code (EDC) Alarm: EDC Read Phase Error Alarm Type: Pulse ALM11[10] Reserved...
  • Page 288 AURIX™ TC33xEXT Safety Management Unit (SMU) Table 179 Alarm Mapping related to ALM20 group (cont’d) Alarm Index Module Safety Mechanism & Alarm Indication ALM20[12] Safety Mechanism: Voltage Monitor Alarm: VDDP3 Under-voltage Alarm Alarm Type: Level ALM20[13] Safety Mechanism: Voltage Monitor Alarm: VDDM Under-voltage Alarm Alarm Type: Level ALM20[14]...

  • Page 289: Connectivity

    AURIX™ TC33xEXT Safety Management Unit (SMU) Table 180 Alarm Mapping related to ALM21 group (cont’d) Alarm Index Module Safety Mechanism & Alarm Indication ALM21[9] Safety Mechanism: Die Temperature Sensor Alarm: Temperature overflow Alarm Type: Level ALM21[10] Safety Mechanism: Register Access Protection Alarm: Access Protection violation Alarm Type: Pulse ALM21[11]...

  • Page 290: Revision History

    AURIX™ TC33xEXT Safety Management Unit (SMU) 15.6 Revision History Table 182 Revision History Reference Change to Previous Version Comment V4.0.17 First release V4.0.18 Page 41 Updated description of ALM21[0] and ALM21[3] Page 41 Added description for ALM21[6] Page 34 Updated description for ALM8[20] Page 1 Missing blank fixed V4.0.19...

  • Page 291: Interrupt Router (Ir)

    AURIX™ TC33xEXT Interrupt Router (IR) Interrupt Router (IR) This chapter supplements the family documentation whith device specific information for TC33xEXT. The Interrupt Router allocates two address ranges • Interrupt Router System and OTGM register address range: 2 * 256 byte address range covering the Interrupt Router system registers, ICU control registers and OTGM registers (Chapter 16.2)

  • Page 292: Tc33Xext Specific Control Registers

    AURIX™ TC33xEXT Interrupt Router (IR) 16.2 TC33xEXT Specific Control Registers This chapter describes the TC33xEXT specific Interrupt Router system, OTGM and ICU registers List of used Access Protection Register abbreviations • P0 -> ACCEN_SRBx, write protection of the related SRBx register. Number of Service Request Broadcast registers (SRB) and the related ACCEN_SRB registers is equal to the number of implemented TriCore CPUs.
  • Page 293 AURIX™ TC33xEXT Interrupt Router (IR) Table 186 Register Overview - INT (ascending Offset Address) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write INT_ID Module Identification 0008 U,SV Application Register Reset Family Spec INT_SRBx Service Request Broadcast 0010 U,SV SV,P0...

  • Page 294: Tc33Xext Specific Registers

    AURIX™ TC33xEXT Interrupt Router (IR) Table 186 Register Overview - INT (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write INT_ACCEN_SRB Access Enable covering 0104 U,SV SV,SE Application SRBx, Register 1 Reset Family (x=0-1) Spec...

  • Page 295: Tc33Xext Specific Service Request Control (Src) Registers

    AURIX™ TC33xEXT Interrupt Router (IR) 16.4 TC33xEXT Specific Service Request Control (SRC) registers This chapter describes the TC33xEXT Service Request Control (SRC) registers. Table 188 shows all registers associated with the Interrupt Router module in the device. This chapter describes the Service Request Control registers including: •...
  • Page 296 AURIX™ TC33xEXT Interrupt Router (IR) Table 188 Register Overview - SRC (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write SRC_ASCLINxER ASCLINx Error Service 00058 U,SV SV,P1,P2 Application Request x*12 Reset (x=0-5) SRC_MTUDONE MTU Done Service Request 000EC...
  • Page 297 AURIX™ TC33xEXT Interrupt Router (IR) Table 188 Register Overview - SRC (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write SRC_DMAERRy DMA Error Service Request y 00340 U,SV SV,P1,P2 Application (y=0-3) Reset SRC_DMACHy DMA Channel y Service 00370...
  • Page 298 AURIX™ TC33xEXT Interrupt Router (IR) Table 188 Register Overview - SRC (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write SRC_RIFxERR Radar Interface x Error 00970 U,SV SV,P1,P2 Application (x=0) Service Request Reset SRC_RIFxINT Radar Interface x Service...

  • Page 299: Tc33Xext Specific Registers

    AURIX™ TC33xEXT Interrupt Router (IR) 16.5 TC33xEXT Specific Registers 16.5.1 IR Service Request Control Registers (SRC) CPUx Software Breakpoint Service Request SRC_CPUxSB (x=0-1) CPUx Software Breakpoint Service Request (00000 + x*4) Debug Reset Value: 0000 0000 SRC_BCUSPB SBCU Service Request [SPB Bus Control Unit) (00020 Debug Reset Value: 0000 0000 SRC_BCUBBB EBCU Service Request [BBB Bus Control Unit, on ED and ADAS devices only)(00024...
  • Page 300 AURIX™ TC33xEXT Interrupt Router (IR) Field Bits Type Description SRPN Service Request Priority Number The SRPN bit field defines the priority of a service request with respect to service requests with to the same service provider (same SRC.TOS configuration): -> Service request is on lowest priority ->...
  • Page 301 AURIX™ TC33xEXT Interrupt Router (IR) Field Bits Type Description Interrupt Trigger Overflow Bit The IOV bit is set by HW if a new service request was triggered via interrupt trigger or SETR bit while the SRN has still an pending service request.
  • Page 302 AURIX™ TC33xEXT Interrupt Router (IR) SRC_QSPIxTX (x=0-3) QSPIx Transmit Service Request (000F0 +x*14 Application Reset Value: 0000 0000 SRC_QSPIxRX (x=0-3) QSPIx Receive Service Request (000F4 +x*14 Application Reset Value: 0000 0000 SRC_QSPIxERR (x=0-3) QSPIx Error Service Request (000F8 +x*14 Application Reset Value: 0000 0000 SRC_QSPIxPT (x=0-3) QSPIx Phase Transition Service Request (000FC...
  • Page 303 AURIX™ TC33xEXT Interrupt Router (IR) Field Bits Type Description 13:11 Type of Service Control The TOS bit field configuration maps a Service Request to an Interrupt Service Provider: CPU0 service is initiated DMA service is initiated CPU1 service is initiated Others, Reserved (no action) 20:16 Error Correction Code...
  • Page 304 AURIX™ TC33xEXT Interrupt Router (IR) Field Bits Type Description SWSCLR SW Sticky Clear Bit SWSCLR is required to reset SWS. No action Clear SWS; bit value is not stored; read always returns 0. 9:8, Reserved 15:14, Read as 0; should be written with 0. 23:21, SRC_GPT120T2 GPT120 Timer 2 Service Request...
  • Page 305 AURIX™ TC33xEXT Interrupt Router (IR) Field Bits Type Description SRPN Service Request Priority Number The SRPN bit field defines the priority of a service request with respect to service requests with to the same service provider (same SRC.TOS configuration): -> Service request is on lowest priority ->...
  • Page 306 AURIX™ TC33xEXT Interrupt Router (IR) Field Bits Type Description Interrupt Trigger Overflow Bit The IOV bit is set by HW if a new service request was triggered via interrupt trigger or SETR bit while the SRN has still an pending service request.
  • Page 307 AURIX™ TC33xEXT Interrupt Router (IR) SRC_SDMMCDMA SDMMC DMA Ready Service Request (00574 Application Reset Value: 0000 0000 SRC_GETHy (y=0-9) GETH Service Request y (00580 +y*4) Application Reset Value: 0000 0000 SRC_CAN0INTy (y=0-15) CAN0 Service Request y (005B0 +y*4) Application Reset Value: 0000 0000 SRC_VADCGxSRy (x=0-5;y=0-3) EVADC Group x Service Request y (00670...
  • Page 308 AURIX™ TC33xEXT Interrupt Router (IR) Field Bits Type Description 13:11 Type of Service Control The TOS bit field configuration maps a Service Request to an Interrupt Service Provider: CPU0 service is initiated DMA service is initiated CPU1 service is initiated Others, Reserved (no action) 20:16 Error Correction Code...
  • Page 309 AURIX™ TC33xEXT Interrupt Router (IR) Field Bits Type Description SWSCLR SW Sticky Clear Bit SWSCLR is required to reset SWS. No action Clear SWS; bit value is not stored; read always returns 0. 9:8, Reserved 15:14, Read as 0; should be written with 0. 23:21, SRC_PMSx (x=0-3) Power Management System Service Request x(008B0...
  • Page 310 AURIX™ TC33xEXT Interrupt Router (IR) Field Bits Type Description SRPN Service Request Priority Number The SRPN bit field defines the priority of a service request with respect to service requests with to the same service provider (same SRC.TOS configuration): -> Service request is on lowest priority ->...
  • Page 311 AURIX™ TC33xEXT Interrupt Router (IR) Field Bits Type Description Interrupt Trigger Overflow Bit The IOV bit is set by HW if a new service request was triggered via interrupt trigger or SETR bit while the SRN has still an pending service request.
  • Page 312 AURIX™ TC33xEXT Interrupt Router (IR) Field Bits Type Description SRPN Service Request Priority Number The SRPN bit field defines the priority of a service request with respect to service requests with to the same service provider (same SRC.TOS configuration): -> Service request is on lowest priority ->...

  • Page 313: Revision History

    AURIX™ TC33xEXT Interrupt Router (IR) Field Bits Type Description Interrupt Trigger Overflow Bit The IOV bit is set by HW if a new service request was triggered via interrupt trigger or SETR bit while the SRN has still an pending service request.
  • Page 314 AURIX™ TC33xEXT Interrupt Router (IR) Table 189 Revision History (cont’d) Reference Change to Previous Version Comment No changes. V1.2.10 – No functional changes. V1.2.11 Page 5 Updated bullet list item. User’s Manual 16-24 V2.0.0 IRV1.2.11 2021-02 OPEN MARKET VERSION...

  • Page 315: Flexible Crc Engine (Fce)

    AURIX™ TC33xEXT Flexible CRC Engine (FCE) Flexible CRC Engine (FCE) For the general description of the module and the registers, please refer to the family spec. 17.1 TC33xEXT Specific IP Configuration There are no device specific IP configurations. User’s Manual 17-1 V2.0.0 FCE V4.2.9...

  • Page 316: Tc33Xext Specific Register Set

    AURIX™ TC33xEXT Flexible CRC Engine (FCE) 17.2 TC33xEXT Specific Register Set Table 190 Register Address Space - FCE Module Base Address End Address Note F0000000 F00001FF FPI slave interface Table 191 Register Overview - FCE (ascending Offset Address) Short Name Long Name Offset Access Mode...

  • Page 317: Tc33Xext Specific Registers

    AURIX™ TC33xEXT Flexible CRC Engine (FCE) Table 191 Register Overview - FCE (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write FCE_LENGTHi CRC Length Register i +i*2 U,SV P,U,SV Application (i=0-7) Reset Family Spec FCE_CHECKi...

  • Page 318: Direct Memory Access (Dma)

    AURIX™ TC33xEXT Direct Memory Access (DMA) Direct Memory Access (DMA) This is the TC33xEXT specific information related to the DMA module of the AURIXTC3XX product family. 18.1 TC33xEXT Specific IP Configuration The TC33xEXT DMA contains 64 DMA channels. 18.2 TC33xEXT Specific Register Set Table 194 Register Address Space - DMA Module...
  • Page 319 AURIX™ TC33xEXT Direct Memory Access (DMA) Table 195 Register Overview - DMA (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write DMA_MEm1R ME m Read Register 1 0144 U,SV Application (m=0-1) *1000 Reset Family Spec...
  • Page 320 AURIX™ TC33xEXT Direct Memory Access (DMA) Table 195 Register Overview - DMA (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write DMA_MEmCHSR ME m Channel Status 019C U,SV Application (m=0-1) Register m*1000 Reset Family Spec...

  • Page 321: Tc33Xext Specific Registers

    AURIX™ TC33xEXT Direct Memory Access (DMA) Table 195 Register Overview - DMA (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write DMA_DADRc DMARAM Channel c 200C U,SV SV,Pr Application (c=000-63) Destination Address Reset Family Register...
  • Page 322 AURIX™ TC33xEXT Direct Memory Access (DMA) User’s Manual 18-5 V2.0.0 DMAV0.1.18 2021-02 OPEN MARKET VERSION...

  • Page 323: Signal Processing Unit (Spu)

    AURIX™ TC33xEXT Signal Processing Unit (SPU) Signal Processing Unit (SPU) This is the device specific information related to the AURIX™ TC33xEXT version of the SPU. 19.1 TC33xEXT Specific IP Configuration There is no specific configuration of the SPU for this device 19.2 TC33xEXT Specific Register Set Table 198...
  • Page 324 AURIX™ TC33xEXT Signal Processing Unit (SPU) Table 199 Register Overview - SPU0 (ascending Offset Address) (cont’d) Short Name Long Name Offset Page Address Number SPU0_ID_RM_IOLR Inner and Outer Loop Repeat 00048 Family Spec SPU0_ID_RM_BLR Bin Loop Repeat 0004C Family Spec SPU0_ID_RM_ACFG0 Spare Configuration Register 00050 Family...
  • Page 325 AURIX™ TC33xEXT Signal Processing Unit (SPU) Table 199 Register Overview - SPU0 (ascending Offset Address) (cont’d) Short Name Long Name Offset Page Address Number SPU0_BEx_SUMCTRL Summation Unit Control 0008C +x*40 (x=0-1) Family Spec SPU0_BEx_PWRSUM Power Summation 00090 +x*40 (x=0-1) Family Spec SPU0_BEx_PWRCTRL Power Information Channel Control...
  • Page 326 AURIX™ TC33xEXT Signal Processing Unit (SPU) Table 199 Register Overview - SPU0 (ascending Offset Address) (cont’d) Short Name Long Name Offset Page Address Number SPU0_SCALARADD Scalar Addition Operand 00200 Family Spec SPU0_SCALARMULT Scalar Multiplication Operand 00204 Family Spec SPU0_BINREJCTRL Bin Rejection Unit Control 00208 Family Spec...
  • Page 327 AURIX™ TC33xEXT Signal Processing Unit (SPU) Table 199 Register Overview - SPU0 (ascending Offset Address) (cont’d) Short Name Long Name Offset Page Address Number SPU0_FFTRCNT FFT Unload Count 00340 Family Spec SPU0_ULDRCNT Output Buffer Memory Write Count 00344 Family Spec SPU0_ODMCNT Output Buffer Memory Read Count 00348...

  • Page 328: Tc33Xext Specific Registers

    AURIX™ TC33xEXT Signal Processing Unit (SPU) Table 199 Register Overview - SPU0 (ascending Offset Address) (cont’d) Short Name Long Name Offset Page Address Number SPU0_ACCEN0 Access Enable Register 0 007E4 Family Spec SPU0_ACCEN1 Access Enable Register 1 007E8 Family Spec SPU0_OCS OCDS Control and Status 007EC...

  • Page 329: Revision History

    AURIX™ TC33xEXT Signal Processing Unit (SPU) 19.5 Revision History Table 201 Revision History Reference Change to Previous Version Comment V1.1.20 Page 7 Previous versions removed from revision history. V1.1.21 Text Insets updated for new tools and source versions. All tables updated. V1.1.22 Text Insets updated as part of document generation flow.

  • Page 330: Spu Lockstep Comparator (Spulckstp)

    AURIX™ TC33xEXT SPU Lockstep Comparator (SPULCKSTP) SPU Lockstep Comparator (SPULCKSTP) This device doesn’t contain a SPULCKSTP module. User’s Manual 20-1 V2.0.0 SPULCKSTP 2021-02 OPEN MARKET VERSION...

  • Page 331: Extended Memory (Emem)

    AURIX™ TC33xEXT Extended Memory (EMEM) Extended Memory (EMEM) This is the TC33xEXT specific information related to the EMEM module of the AURIXTC3XX product family. 21.1 TC33xEXT Specific IP Configuration The TC33xEXT EMEM contains 1 Mbyte of extension memory in one instance of the EMEM module. 21.2 TC33xEXT Specific Register Set Table 202...
  • Page 332 AURIX™ TC33xEXT Extended Memory (EMEM) Table 206 Register Overview - EMEM (ascending Offset Address) Short Name Description Offset Access Mode Page Address Number Read Write EMEM_CLC EMEM Core Clock Control Register 0000 U,SV SV,E,P Family Spec EMEM_ID EMEM Core Module Identification Register 0008 U,SV Family...

  • Page 333: Tc33Xext Specific Registers

    AURIX™ TC33xEXT Extended Memory (EMEM) Table 207 Register Overview - EMEMMPU0 (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write EMEMMPU0_ACC EMEM Module Access 00014 SV,SE Application Enable Register 1 Reset Family Spec EMEMMPU0_ME EMEM Module Memory...

  • Page 334: Revision History

    AURIX™ TC33xEXT Extended Memory (EMEM) 21.5 Revision History Table 208 Revision History Reference Change to Previous Version Comment V1.3.13 Initial version for TC33X. V1.3.14 Page 1 Correction of configuration size in chapter 1.1 V1.4.1 Page 2 Add extra registers TILESTATE1 and TILECONFIG1 to support increased memory size.

  • Page 335: Radar Interface (Rif)

    AURIX™ TC33xEXT Radar Interface (RIF) Radar Interface (RIF) This chapter describes the Radar Interface (RIF) module of the TC33xEXT. 22.1 TC33xEXT Specific IP Configuration See features in the family spec. Table 209 TC33xEXT specific configuration of RIF Parameter RIF0 Software Triggered Reset of the Module Kernel Kernel Reset (software controlled by KRST0-1 This reset does not affect the bus interfaces and therefore registers)

  • Page 336: Revision History

    AURIX™ TC33xEXT Radar Interface (RIF) Table 212 Connections of RIF0 (cont’d) Interface Signals connects Description RIF0:D1N from TC33xEXT:P50.0 LVDS RX Input (inverted Data Bits of Channel RIF0:D2N from TC33xEXT:P50.2 LVDS RX Input (inverted Data Bits of Channel RIF0:D3N from TC33xEXT:P50.8 LVDS RX Input (inverted Data Bits of Channel RIF0:D4N from TC33xEXT:P50.10...
  • Page 337 AURIX™ TC33xEXT Radar Interface (RIF) Table 213 Revision History Reference Change to Previous Version Comment – Device specific register, RIF0_ESI is moved from the family spec to the appendix. – No functional changes. – V1.0.41 – No functional changes. – V1.0.42 –...

  • Page 338: High Speed Pulse Density Modulation Module (Hspdm)

    AURIX™ TC33xEXT High Speed Pulse Density Modulation Module (HSPDM) High Speed Pulse Density Modulation Module (HSPDM) Text with reference to family spec. 23.1 TC33xEXT Specific IP Configuration See features in the family spec. Table 214 TC33xEXT specific configuration of HSPDM Parameter HSPDM HSPDM ram...

  • Page 339: Pinning And Layout

    AURIX™ TC33xEXT High Speed Pulse Density Modulation Module (HSPDM) Radar ECU Radar ECU Module Module Single Software INT15 INT15 START Write T13HRE T13HRE CCU6 CCU6 DELAY DELAY1 (=0) DELAY2 COUT63 COUT63 interrupt Software HWRUN HWRUN clear HSPDM HSPDM Figure 6 Hardware Run Connections 23.4.2 Pinning and Layout...

  • Page 340: Camera And Adc Interface (Cif)

    AURIX™ TC33xEXT Camera and ADC Interface (CIF) Camera and ADC Interface (CIF) This device doesn’t contain a CIF module. User’s Manual 24-1 V2.0.0 2021-02 OPEN MARKET VERSION...

  • Page 341: System Timer (Stm)

    AURIX™ TC33xEXT System Timer (STM) System Timer (STM) This chapter describes the device specific details in TC33xEXT. 25.1 TC33xEXT Specific IP Configuration See features in family spec 25.2 TC33xEXT Specific Register Set Register Address Space Table The address space for the module registers is defined below Table 217 Register Address Space - STM Module Base Address...

  • Page 342: Revision History

    AURIX™ TC33xEXT System Timer (STM) 25.5 Revision History Table 220 Revision History Reference Change to Previous Version Comment V9.2.3 – Initial version for TC33X. V9.2.4 Page 1 Connection tables updated (no functional changes). User’s Manual 25-2 V2.0.0 STMV9.2.4 2021-02 OPEN MARKET VERSION...

  • Page 343: Generic Timer Module (Gtm)

    AURIX™ TC33xEXT Generic Timer Module (GTM) Generic Timer Module (GTM) This device doesn’t contain a GTM. User’s Manual 26-1 V2.0.0 2021-02 OPEN MARKET VERSION...

  • Page 344: Capture/Compare Unit 6 (Ccu6)

    AURIX™ TC33xEXT Capture/Compare Unit 6 (CCU6) Capture/Compare Unit 6 (CCU6) This chapter describes the specific properties of the product TC33xEXT, which is a member of the product family TC3XX. The functionality of the CCU6 is described in the TC3XX family documentation. The complete product description consists of the family documentation and this product-specific appendix.
  • Page 345 AURIX™ TC33xEXT Capture/Compare Unit 6 (CCU6) Table 222 Register Overview - CCU60 (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write CCU60_T12PR Timer 12 Period Register 0024 U,SV U,SV,P Application Reset Family Spec CCU60_T12DTC Dead-Time Control Register...
  • Page 346 AURIX™ TC33xEXT Capture/Compare Unit 6 (CCU6) Table 222 Register Overview - CCU60 (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write CCU60_MODCTR Modulation Control Register 0080 U,SV U,SV,P Application Reset Family Spec CCU60_TRPCTR Trap Control Register 0084...
  • Page 347 AURIX™ TC33xEXT Capture/Compare Unit 6 (CCU6) Table 222 Register Overview - CCU60 (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write CCU60_KRSTCLR Kernel Reset Status Clear 00EC U,SV SV,E,P Application Register Reset Family Spec CCU60_KRST1...
  • Page 348 AURIX™ TC33xEXT Capture/Compare Unit 6 (CCU6) Table 223 Register Overview - CCU61 (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write CCU61_T12DTC Dead-Time Control Register 0028 U,SV U,SV,P Application for Timer12 Reset Family Spec CCU61_CC6xR...
  • Page 349 AURIX™ TC33xEXT Capture/Compare Unit 6 (CCU6) Table 223 Register Overview - CCU61 (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write CCU61_TRPCTR Trap Control Register 0084 U,SV U,SV,P Application Reset Family Spec CCU61_PSLR Passive State Level Register 0088 U,SV...

  • Page 350: Tc33Xext Specific Registers

    AURIX™ TC33xEXT Capture/Compare Unit 6 (CCU6) Table 223 Register Overview - CCU61 (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write CCU61_KRST1 Kernel Reset Register 1 00F0 U,SV SV,E,P Application Reset Family Spec CCU61_KRST0 Kernel Reset Register 0...
  • Page 351 AURIX™ TC33xEXT Capture/Compare Unit 6 (CCU6) Table 224 Connections of CCU60 (cont’d) Interface Signals connects Description CCU60:CC60IND from PMS:pms_wut_underflo T12 capture input 60 CCU60:CC62IND from SCU:E_PDOUT(4) T12 capture input 62 CCU60:CCPOS0A from P02.6:IN Hall capture input 0 CCU60:CCPOS1A from P02.7:IN Hall capture input 1 CCU60:CCPOS2A from P02.8:IN...
  • Page 352 AURIX™ TC33xEXT Capture/Compare Unit 6 (CCU6) Table 224 Connections of CCU60 (cont’d) Interface Signals connects Description CCU60:SR(3) EVADC:G0REQTRA Service request EVADC:G1REQTRA EVADC:G2REQTRA EVADC:G3REQTRA EVADC:G4REQTRA EVADC:G5REQTRA CCU60:T12HRA from SCU:scu_cctrig0 External timer start 12 CCU60:T13HRA from SCU:scu_cctrig0 External timer start 13 CCU60:T12HRB from P00.7:IN External timer start 12 CCU60:T13HRB...
  • Page 353 AURIX™ TC33xEXT Capture/Compare Unit 6 (CCU6) Table 225 Connections of CCU61 Interface Signals connects Description CCU61:CC60 P00.1:ALT(7) T12 PWM channel 60 P00.7:ALT(7) P20.8:ALT(7) P33.13:ALT(7) CCU61:CC61 P00.3:ALT(7) T12 PWM channel 61 P00.8:ALT(7) P20.9:ALT(7) P33.11:ALT(7) CCU61:CC62 P00.5:ALT(7) T12 PWM channel 62 P00.9:ALT(7) P20.10:ALT(7) P33.9:ALT(7) CCU61:CC60INA...
  • Page 354 AURIX™ TC33xEXT Capture/Compare Unit 6 (CCU6) Table 225 Connections of CCU61 (cont’d) Interface Signals connects Description CCU61:COUT61 P00.4:ALT(7) T12 PWM channel 61 P20.12:ALT(7) P33.10:ALT(7) CCU61:COUT62 P00.6:ALT(7) T12 PWM channel 62 P20.13:ALT(7) P33.8:ALT(7) CCU61:COUT63 HSPDM:HWRUN(0) T13 PWM channel 63 P00.12:ALT(7) P20.7:ALT(7) CCU61:CTRAPA from P00.0:IN Trap input capture...

  • Page 355: Revision History

    AURIX™ TC33xEXT Capture/Compare Unit 6 (CCU6) 27.4 Revision History Table 226 Revision History Reference Change to Previous Version Comment V3.0.0 Initial release. User’s Manual 27-12 V2.0.0 CCU6 V3.0.0 2021-02 OPEN MARKET VERSION...

  • Page 356: General Purpose Timer Unit (Gpt12)

    AURIX™ TC33xEXT General Purpose Timer Unit (GPT12) General Purpose Timer Unit (GPT12) This chapter describes the specific properties of the product TC33xEXT, which is a member of the product family TC3XX. The functionality of the GPT12 is described in the TC3XX family documentation. The complete product description consists of the family documentation and this product-specific appendix.

  • Page 357: Connectivity

    AURIX™ TC33xEXT General Purpose Timer Unit (GPT12) 28.3 Connectivity Table 228 Connections of GPT120 Interface Signals connects Description GPT120:CAPINB from SCU:E_PDOUT(6) Trigger input to capture value of timer T5 into CAPREL register GPT120:T2EUDA from P00.8:IN Count direction control input of timer T2 GPT120:T3EUDA from P02.7:IN Count direction control input of core timer T3...

  • Page 358: Revision History

    AURIX™ TC33xEXT General Purpose Timer Unit (GPT12) Table 228 Connections of GPT120 (cont’d) Interface Signals connects Description GPT120:T3_INT INT:gpt120.T3_INT GPT120 T3 Overflow/Underflow Service Request GPT120:T4_INT INT:gpt120.T4_INT GPT120 T4 Overflow/Underflow Service Request GPT120:T5_INT INT:gpt120.T5_INT GPT120 T5 Overflow/Underflow Service Request GPT120:T6_INT INT:gpt120.T6_INT GPT120 T6 Overflow/Underflow Service Request 28.4...

  • Page 359: Converter Control Block (Convctrl)

    AURIX™ TC33xEXT Converter Control Block (CONVCTRL) Converter Control Block (CONVCTRL) This chapter describes the specific properties of the product TC33xEXT, which is a member of the product family TC3xx. The functionality of the CONVCTRL is described in the TC3xx family documentation. The complete product description consists of the family documentation and this product-specific appendix.

  • Page 360: Connectivity

    AURIX™ TC33xEXT Converter Control Block (CONVCTRL) 29.4 Connectivity The CONVCTRL is connected to its environment through a number of input and output signals. Table 232 Digital Connections for Product TC33xEXT Signal Dir. Source/Destin. Description General PHSYNC EVADC Synchronization signal for analog clocks CC_ALARM Alarm signal from safety logic Table 233 List of CONVERTER Interface Signals...

  • Page 361: Enhanced Versatile Analog-To-Digital Converter (Evadc)

    AURIX™ TC33xEXT Enhanced Versatile Analog-to-Digital Converter (EVADC) Enhanced Versatile Analog-to-Digital Converter (EVADC) This chapter describes the specific properties of the product TC33xEXT, which is a member of the product family TC3XX. The functionality of the EVADC is described in the TC3XX family documentation. The complete product description consists of the family documentation and this product-specific appendix.

  • Page 362: Tc33Xext Specific Register Set

    AURIX™ TC33xEXT Enhanced Versatile Analog-to-Digital Converter (EVADC) 2) Control input CI0 always selects the own control signals of the corresponding ADC kernel. This selection is meant for the synchronization master or for stand-alone operation. Table 237 TC33xEXT specific configuration of EVADC Parameter EVADC Number of available primary groups...

  • Page 363: Connectivity

    AURIX™ TC33xEXT Enhanced Versatile Analog-to-Digital Converter (EVADC) 30.3 Connectivity The EVADC is connected to its environment through a number of analog input signals and also digital input and output signals. These connections establish communication with other peripherals, with the system blocks, and with external components.
  • Page 364 AURIX™ TC33xEXT Enhanced Versatile Analog-to-Digital Converter (EVADC) Table 239 Analog Input Connections for Product TC33xEXT (cont’d) Signal Source Overlay Description Analog Inputs for Group 1 (Primary) G1CH0 (AltRef) G5CH4 analog input channel 0 of group 1 G1CH1 (MD) G5CH5 analog input channel 1 of group 1 G1CH2 (MD) AN10 G5CH6...
  • Page 365 AURIX™ TC33xEXT Enhanced Versatile Analog-to-Digital Converter (EVADC) Table 239 Analog Input Connections for Product TC33xEXT (cont’d) Signal Source Overlay Description G5CH1 (MD) G0CH5 analog input channel 1 of group 5 G5CH2 (MD) G0CH6 analog input channel 2 of group 5 G5CH3 G0CH7 analog input channel 3 of group 5...

  • Page 366: Digital Module Connections

    AURIX™ TC33xEXT Enhanced Versatile Analog-to-Digital Converter (EVADC) 30.3.2 Digital Module Connections The EVADC module accepts a number of digital input signals and generates a number of output signals. This section summarizes the connection of these signals to other on-chip modules or to external resources via port pins.
  • Page 367 AURIX™ TC33xEXT Enhanced Versatile Analog-to-Digital Converter (EVADC) Table 240 Digital Connections for Product TC33xEXT (cont’d) Signal Dir. Source/Destin. Description GxREQTRO vadc_c1sr1 [1110 ] Service request 1, common group 1 GxREQTRyP GxREQGTySEL [1111 ] Extend triggers to selected gating input of the respective source GxREQTRySEL Selected trigger signal of the respective source...

  • Page 368: Revision History

    AURIX™ TC33xEXT Enhanced Versatile Analog-to-Digital Converter (EVADC) 30.4 Revision History This is a summary of the modifications that have been applied to this chapter. Table 241 Revision History Reference Change to Previous Version Comment V3.0.0 – Initial version. – V3.0.1 Page 1 Footnote added to table General Converter Configuration TC33xEXT...

  • Page 369: Enhanced Delta-Sigma Analog-To-Digital Converter (Edsadc)

    AURIX™ TC33xEXT Enhanced Delta-Sigma Analog-to-Digital Converter (EDSADC) Enhanced Delta-Sigma Analog-to-Digital Converter (EDSADC) This device doesn’t contain an EDSADC. User’s Manual 31-1 V2.0.0 EDSADC 2021-02 OPEN MARKET VERSION...

  • Page 370: Inter-Integrated Circuit (I2C)

    AURIX™ TC33xEXT Inter-Integrated Circuit (I2C) Inter-Integrated Circuit (I2C) This device doesn’t contain an I2C. User’s Manual 32-1 V2.0.0 2021-02 OPEN MARKET VERSION...

  • Page 371: High Speed Serial Link (Hssl)

    AURIX™ TC33xEXT High Speed Serial Link (HSSL) High Speed Serial Link (HSSL) This device doesn’t contain a HSSL. User’s Manual 33-1 V2.0.0 HSSL 2021-02 OPEN MARKET VERSION...

  • Page 372: Asynchronous Serial Interface (Asclin)

    AURIX™ TC33xEXT Asynchronous Serial Interface (ASCLIN) Asynchronous Serial Interface (ASCLIN) Text with reference to family spec. 34.1 TC33xEXT Specific IP Configuration No product specific configuration for ASCLIN User’s Manual 34-1 V2.0.0 ASCLINV3.2.8 2021-02 OPEN MARKET VERSION...

  • Page 373: Tc33Xext Specific Register Set

    AURIX™ TC33xEXT Asynchronous Serial Interface (ASCLIN) 34.2 TC33xEXT Specific Register Set Register Address Space Table Table 242 Register Address Space - ASCLIN Module Base Address End Address Note ASCLIN0 F0000600 F00006FF FPI slave interface ASCLIN1 F0000700 F00007FF FPI slave interface ASCLIN2 F0000800 F00008FF...
  • Page 374 AURIX™ TC33xEXT Asynchronous Serial Interface (ASCLIN) Table 243 Register Overview - ASCLIN (ascending Offset Address) (cont’d) Short Name Long Name Offset Page Address Number ASCLIN2_IOCR Input and Output Control Register Family Spec ASCLIN3_IOCR Input and Output Control Register Family Spec ASCLIN4_IOCR Input and Output Control Register Family...
  • Page 375 AURIX™ TC33xEXT Asynchronous Serial Interface (ASCLIN) Table 243 Register Overview - ASCLIN (ascending Offset Address) (cont’d) Short Name Long Name Offset Page Address Number ASCLIN4_TXFIFOCON TX FIFO Configuration Register Family Spec ASCLIN5_TXFIFOCON TX FIFO Configuration Register Family Spec ASCLIN0_RXFIFOCON RX FIFO Configuration Register Family Spec ASCLIN1_RXFIFOCON RX FIFO Configuration Register...
  • Page 376 AURIX™ TC33xEXT Asynchronous Serial Interface (ASCLIN) Table 243 Register Overview - ASCLIN (ascending Offset Address) (cont’d) Short Name Long Name Offset Page Address Number ASCLIN0_FRAMECON Frame Control Register Family Spec ASCLIN1_FRAMECON Frame Control Register Family Spec ASCLIN2_FRAMECON Frame Control Register Family Spec ASCLIN3_FRAMECON Frame Control Register...
  • Page 377 AURIX™ TC33xEXT Asynchronous Serial Interface (ASCLIN) Table 243 Register Overview - ASCLIN (ascending Offset Address) (cont’d) Short Name Long Name Offset Page Address Number ASCLIN2_BRG Baud Rate Generation Register Family Spec ASCLIN3_BRG Baud Rate Generation Register Family Spec ASCLIN4_BRG Baud Rate Generation Register Family Spec ASCLIN5_BRG...
  • Page 378 AURIX™ TC33xEXT Asynchronous Serial Interface (ASCLIN) Table 243 Register Overview - ASCLIN (ascending Offset Address) (cont’d) Short Name Long Name Offset Page Address Number ASCLIN4_LINCON LIN Control Register Family Spec ASCLIN5_LINCON LIN Control Register Family Spec ASCLIN0_LINBTIMER LIN Break Timer Register Family Spec ASCLIN1_LINBTIMER LIN Break Timer Register...
  • Page 379 AURIX™ TC33xEXT Asynchronous Serial Interface (ASCLIN) Table 243 Register Overview - ASCLIN (ascending Offset Address) (cont’d) Short Name Long Name Offset Page Address Number ASCLIN0_FLAGS Flags Register Family Spec ASCLIN1_FLAGS Flags Register Family Spec ASCLIN2_FLAGS Flags Register Family Spec ASCLIN3_FLAGS Flags Register Family Spec...
  • Page 380 AURIX™ TC33xEXT Asynchronous Serial Interface (ASCLIN) Table 243 Register Overview - ASCLIN (ascending Offset Address) (cont’d) Short Name Long Name Offset Page Address Number ASCLIN2_FLAGSCLEA Flags Clear Register Family Spec ASCLIN3_FLAGSCLEA Flags Clear Register Family Spec ASCLIN4_FLAGSCLEA Flags Clear Register Family Spec ASCLIN5_FLAGSCLEA...
  • Page 381 AURIX™ TC33xEXT Asynchronous Serial Interface (ASCLIN) Table 243 Register Overview - ASCLIN (ascending Offset Address) (cont’d) Short Name Long Name Offset Page Address Number ASCLIN4_TXDATA Transmit Data Register Family Spec ASCLIN5_TXDATA Transmit Data Register Family Spec ASCLIN0_RXDATA Receive Data Register Family Spec ASCLIN1_RXDATA...
  • Page 382 AURIX™ TC33xEXT Asynchronous Serial Interface (ASCLIN) Table 243 Register Overview - ASCLIN (ascending Offset Address) (cont’d) Short Name Long Name Offset Page Address Number ASCLIN0_RXDATAD Receive Data Debug Register Family Spec ASCLIN1_RXDATAD Receive Data Debug Register Family Spec ASCLIN2_RXDATAD Receive Data Debug Register Family Spec ASCLIN3_RXDATAD...
  • Page 383 AURIX™ TC33xEXT Asynchronous Serial Interface (ASCLIN) Table 243 Register Overview - ASCLIN (ascending Offset Address) (cont’d) Short Name Long Name Offset Page Address Number ASCLIN2_KRSTCLR Kernel Reset Status Clear Register Family Spec ASCLIN3_KRSTCLR Kernel Reset Status Clear Register Family Spec ASCLIN4_KRSTCLR Kernel Reset Status Clear Register Family...
  • Page 384 AURIX™ TC33xEXT Asynchronous Serial Interface (ASCLIN) Table 243 Register Overview - ASCLIN (ascending Offset Address) (cont’d) Short Name Long Name Offset Page Address Number ASCLIN4_KRST0 Kernel Reset Register 0 Family Spec ASCLIN5_KRST0 Kernel Reset Register 0 Family Spec ASCLIN0_ACCEN1 Access Enable Register 1 Family Spec ASCLIN1_ACCEN1...

  • Page 385: Tc33Xext Specific Registers

    AURIX™ TC33xEXT Asynchronous Serial Interface (ASCLIN) 34.3 TC33xEXT Specific Registers No deviations from the Family Spec 34.4 Connectivity Table 244 Connections of ASCLIN0 Interface Signals connects Description ASCLIN0:ACTSA from P14.9:IN Clear to send input ASCLIN0:ACTSD from ASCLIN0:ARTS Clear to send input ASCLIN0:ARTS P14.7:ALT(2) Ready to send output...
  • Page 386 AURIX™ TC33xEXT Asynchronous Serial Interface (ASCLIN) Table 245 Connections of ASCLIN1 (cont’d) Interface Signals connects Description ASCLIN1:ARXF from P33.13:IN Receive input ASCLIN1:ARXG from P02.3:IN Receive input ASCLIN1:ASCLK P15.0:ALT(6) Shift clock output P20.10:ALT(6) P33.11:ALT(2) P33.12:ALT(4) ASCLIN1:ASLSO P14.3:ALT(4) Slave select signal output P20.8:ALT(2) P33.10:ALT(4) ASCLIN1:ATX...
  • Page 387 AURIX™ TC33xEXT Asynchronous Serial Interface (ASCLIN) Table 246 Connections of ASCLIN2 (cont’d) Interface Signals connects Description ASCLIN2:ASCLK P02.4:ALT(2) Shift clock output P10.6:ALT(2) P14.2:ALT(6) P33.7:ALT(2) P33.9:ALT(4) ASCLIN2:ASLSO P02.3:ALT(2) Slave select signal output P10.5:ALT(6) P33.6:ALT(2) ASCLIN2:ATX P02.0:ALT(2) Transmit output P10.5:ALT(2) P14.2:ALT(2) P14.3:ALT(2) P33.8:ALT(2) P33.9:ALT(2) ASCLIN2:sleep_n...
  • Page 388 AURIX™ TC33xEXT Asynchronous Serial Interface (ASCLIN) Table 247 Connections of ASCLIN3 (cont’d) Interface Signals connects Description ASCLIN3:ASCLK P00.0:ALT(2) Shift clock output P00.2:ALT(2) P11.1:ALT(2) P11.4:ALT(2) P15.6:ALT(6) P15.8:ALT(6) P20.0:ALT(3) P21.5:ALT(2) P21.7:ALT(3) P33.2:ALT(2) ASCLIN3:ASLSO P00.3:ALT(2) Slave select signal output P12.1:ALT(2) P14.3:ALT(5) P21.2:ALT(2) P21.6:ALT(2) P33.1:ALT(2) ASCLIN3:ATX P00.0:ALT(3)

  • Page 389: Revision History

    AURIX™ TC33xEXT Asynchronous Serial Interface (ASCLIN) Table 248 Connections of ASCLIN4 (cont’d) Interface Signals connects Description ASCLIN4:ATX P00.9:ALT(5) Transmit output P22.5:ALT(2) P34.1:ALT(2) ASCLIN4:sleep_n from SCU:scu_syst_sleep_n Negative turn-off request ASCLIN4:TX_INT INT:asclin4.TX_INT ASCLIN Transmit Service Request ASCLIN4:RX_INT INT:asclin4.RX_INT ASCLIN Receive Service Request ASCLIN4:ERR_INT INT:asclin4.ERR_INT ASCLIN Error Service Request...

  • Page 390: Queued Synchronous Peripheral Interface (Qspi)

    AURIX™ TC33xEXT Queued Synchronous Peripheral Interface (QSPI) Queued Synchronous Peripheral Interface (QSPI) 35.1 TC33xEXT Specific IP Configuration Table 251 TC33xEXT specific configuration of QSPI Parameter QSPI0 QSPI1 QSPI2 QSPI3 QSPI module has HSIC User’s Manual 35-1 V2.0.0 QSPIV3.0.20 2021-02 OPEN MARKET VERSION...

  • Page 391: Tc33Xextspecific Register Set

    AURIX™ TC33xEXT Queued Synchronous Peripheral Interface (QSPI) 35.2 TC33xEXTSpecific Register Set Register Address Space Table Table 252 Register Address Space - QSPI Module Base Address End Address Note QSPI0 F0001C00 F0001CFF Register block QSPI0 QSPI1 F0001D00 F0001DFF Register block QSPI1 QSPI2 F0001E00 F0001EFF...
  • Page 392 AURIX™ TC33xEXT Queued Synchronous Peripheral Interface (QSPI) Table 253 Register Overview - QSPI0 (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write QSPI0_SSOC Slave Select Output Control U,SV SV,P Application Register Reset Family Spec QSPI0_FLAGSCLE...
  • Page 393 AURIX™ TC33xEXT Queued Synchronous Peripheral Interface (QSPI) Table 253 Register Overview - QSPI0 (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write QSPI0_ACCEN1 Access Enable Register 1 U,SV SV,SE Application Reset Family Spec QSPI0_ACCEN0 Access Enable Register 0...
  • Page 394 AURIX™ TC33xEXT Queued Synchronous Peripheral Interface (QSPI) Table 254 Register Overview - QSPI1 (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write QSPI1_XXLCON Extra Large Data U,SV U,SV,P Application Configuration Register Reset Family Spec QSPI1_MIXENTRY MIX_ENTRY Register...
  • Page 395 AURIX™ TC33xEXT Queued Synchronous Peripheral Interface (QSPI) Table 255 Register Overview - QSPI2 (ascending Offset Address) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write QSPI2_CLC Clock Control Register U,SV SV,E,P Application Reset Family Spec QSPI2_PISEL Port Input Select Register U,SV SV,P...
  • Page 396 AURIX™ TC33xEXT Queued Synchronous Peripheral Interface (QSPI) Table 255 Register Overview - QSPI2 (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write QSPI2_DATAENT DATA_ENTRY Register x U,SV U,SV,P Application Reset Family (x=0-7) Spec QSPI2_RXEXIT RX_EXIT Register...
  • Page 397 AURIX™ TC33xEXT Queued Synchronous Peripheral Interface (QSPI) Table 256 Register Overview - QSPI3 (ascending Offset Address) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write QSPI3_CLC Clock Control Register U,SV SV,E,P Application Reset Family Spec QSPI3_PISEL Port Input Select Register U,SV SV,P...
  • Page 398 AURIX™ TC33xEXT Queued Synchronous Peripheral Interface (QSPI) Table 256 Register Overview - QSPI3 (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write QSPI3_DATAENT DATA_ENTRY Register x U,SV U,SV,P Application Reset Family (x=0-7) Spec QSPI3_RXEXIT RX_EXIT Register...

  • Page 399: Tc33Xext Specific Registers

    AURIX™ TC33xEXT Queued Synchronous Peripheral Interface (QSPI) 35.3 TC33xEXT Specific Registers 35.3.1 Register block QSPI Port Input Select Register The PISEL register controls the input signal selection of the SSC module. QSPI0_PISEL Port Input Select Register (004 Application Reset Value: 0000 0000 SLSIS SCIS SRIS...
  • Page 400 AURIX™ TC33xEXT Queued Synchronous Peripheral Interface (QSPI) Field Bits Type Description SLSIS 14:12 Slave Mode Slave Select Input Selection The SLSIS must be programmed properly before the slave mode is set with GLOBALCON.MODE and the module is set to RUN mode. The following signal sources are available in this product (if supported by the package!) no input...
  • Page 401 AURIX™ TC33xEXT Queued Synchronous Peripheral Interface (QSPI) Field Bits Type Description SCIS 10:8 Slave Mode Clock Input Select SCIS selects one out of eight module kernel SCLK input lines that is used as clock input line in slave mode. Note that not all inputs are used in every device of the family.
  • Page 402 AURIX™ TC33xEXT Queued Synchronous Peripheral Interface (QSPI) Field Bits Type Description SRIS Slave Mode Receive Input Select SRIS selects one out of eight MTSR receive input lines, used in Slave Mode. Note that not all inputs are used in every device of the family. Selecting an unused input returns a continuous low value.

  • Page 403: Connectivity

    AURIX™ TC33xEXT Queued Synchronous Peripheral Interface (QSPI) Field Bits Type Description MRIS Master Mode Receive Input Select MRIS selects one out of eight MRST receive input lines, used in Master Mode. Note that not all inputs are used in every device of the family. Selecting an unused input returns a continuous low value.
  • Page 404 AURIX™ TC33xEXT Queued Synchronous Peripheral Interface (QSPI) Table 257 Connections of QSPI0 (cont’d) Interface Signals connects Description QSPI0:MTSR P20.12:ALT(4) Master SPI data output P20.14:ALT(3) P22.5:ALT(4) QSPI0:MTSRA from P20.14:IN Slave SPI data input QSPI0:MTSRC from P22.5:IN Slave SPI data input QSPI0:SCLK P20.11:ALT(3) Master SPI clock output P20.13:ALT(5)
  • Page 405 AURIX™ TC33xEXT Queued Synchronous Peripheral Interface (QSPI) Table 258 Connections of QSPI1 (cont’d) Interface Signals connects Description QSPI1:MTSR P10.1:ALT(2) Master SPI data output P10.3:ALT(3) P10.4:ALT(4) P11.9:ALT(3) QSPI1:MTSRA from P10.3:IN Slave SPI data input QSPI1:MTSRB from P11.9:IN Slave SPI data input QSPI1:MTSRC from P10.4:IN Slave SPI data input...
  • Page 406 AURIX™ TC33xEXT Queued Synchronous Peripheral Interface (QSPI) Table 259 Connections of QSPI2 (cont’d) Interface Signals connects Description QSPI2:MRSTE from P15.2:IN Master SPI data input QSPI2:MTSR P15.5:ALT(3) Master SPI data output P15.6:ALT(3) QSPI2:MTSRA from P15.5:IN Slave SPI data input QSPI2:MTSRB from P15.6:IN Slave SPI data input QSPI2:SCLK P15.3:ALT(3)

  • Page 407: Revision History

    AURIX™ TC33xEXT Queued Synchronous Peripheral Interface (QSPI) Table 260 Connections of QSPI3 (cont’d) Interface Signals connects Description QSPI3:MRST P02.5:ALT(3) Slave SPI data output P10.7:ALT(3) QSPI3:MRSTA from P02.5:IN Master SPI data input QSPI3:MRSTB from P10.7:IN Master SPI data input QSPI3:MTSR P02.6:ALT(3) Master SPI data output P10.6:ALT(3) QSPI3:MTSRA...

  • Page 408: Micro Second Channel (Msc)

    AURIX™ TC33xEXT Micro Second Channel (MSC) Micro Second Channel (MSC) This device doesn’t contain a MSC. User’s Manual 36-1 V2.0.0 2021-02 OPEN MARKET VERSION...

  • Page 409: Single Edge Nibble Transmission (Sent)

    AURIX™ TC33xEXT Single Edge Nibble Transmission (SENT) Single Edge Nibble Transmission (SENT) This document describes the SENT Interface specific appendix for the product TC33xEXT. 37.1 TC33xEXT Specific IP Configuration See features in family spec. Table 262 TC33xEXT specific configuration of SENT Parameter SENT Number of SENT channels for this device...

  • Page 410: Tc33Xext Specific Register Set

    AURIX™ TC33xEXT Single Edge Nibble Transmission (SENT) 37.2 TC33xEXT Specific Register Set Register Address Space Table The address space for the module registers is defined in Register Address Space Table. Table 263 Register Address Space - SENT Module Base Address End Address Note SENT...

  • Page 411: Revision History

    AURIX™ TC33xEXT Single Edge Nibble Transmission (SENT) Table 264 Connections of SENT (cont’d) Interface Signals connects Description SENT:SENT4C from P33.6:IN Receive input channel 4 SENT:SENT5C from P33.5:IN Receive input channel 5 SENT:SPC(0) P00.1:ALT(6) Transmit output SENT:SPC(1) P02.7:ALT(6) Transmit output SENT:SPC(2) P00.3:ALT(6) Transmit output SENT:SPC(3)

  • Page 412: Can Interface (Mcmcan)

    AURIX™ TC33xEXT CAN Interface (MCMCAN) CAN Interface (MCMCAN) This section describes the MCMCAN Interface specific appendix for the product TC33xEXT. 38.1 TC33xEXT Specific IP Configuration Table 266 TC33xEXT specific configuration of CAN Parameter CAN0 Node size in byte 1024 Number of CAN Nodes RAM size in byte 32768 Maximum Number of Standard ID Filter Messages per...

  • Page 413: Tc33Xext Specific Register Set

    AURIX™ TC33xEXT CAN Interface (MCMCAN) 38.2 TC33xEXT Specific Register Set Register Address Space Table Table 267 Register Address Space - CAN Module Base Address End Address Note CAN0 F0200000 F0208FFF Bus Interface Register Overview Table Table 268 Register Overview - CAN (ascending Offset Address) Short Name Long Name Offset...
  • Page 414 AURIX™ TC33xEXT CAN Interface (MCMCAN) Table 268 Register Overview - CAN (ascending Offset Address) (cont’d) Short Name Long Name Offset Page Address Number CAN0_KRST1 Kernel Reset Register 1 0080F0 Family Spec CAN0_KRST0 Kernel Reset Register 0 0080F4 Family Spec CAN0_ACCEN0 Access Enable Register 0 0080FC Family...
  • Page 415 AURIX™ TC33xEXT CAN Interface (MCMCAN) Table 268 Register Overview - CAN (ascending Offset Address) (cont’d) Short Name Long Name Offset Page Address Number CAN0_NPCRi Node i Port Control Register 008140 +i*400 (i=0-3) Family Spec CAN0_CRELi Core Release Register i 008200 +i*400 (i=0-3) Family...
  • Page 416 AURIX™ TC33xEXT CAN Interface (MCMCAN) Table 268 Register Overview - CAN (ascending Offset Address) (cont’d) Short Name Long Name Offset Page Address Number CAN0_TDCRi Transmitter Delay Compensation Register i 008248 +i*400 (i=0-3) Family Spec CAN0_IRi Interrupt Register i 008250 +i*400 (i=0-3) Family Spec...
  • Page 417 AURIX™ TC33xEXT CAN Interface (MCMCAN) Table 268 Register Overview - CAN (ascending Offset Address) (cont’d) Short Name Long Name Offset Page Address Number CAN0_RXF1Ci Rx FIFO 1 Configuration i 0082B0 +i*40 (i=0-3) Family Spec CAN0_RXF1Si Rx FIFO 1 Status i 0082B4 +i*40 (i=0-3)

  • Page 418: Tc33Xext Specific Registers

    AURIX™ TC33xEXT CAN Interface (MCMCAN) Table 268 Register Overview - CAN (ascending Offset Address) (cont’d) Short Name Long Name Offset Page Address Number CAN0_TXEFCi Tx Event FIFO Configuration i 0082F0 +i*400 (i=0-3) Family Spec CAN0_TXEFSi Tx Event FIFO Status i 0082F4 +i*400 (i=0-3)
  • Page 419 AURIX™ TC33xEXT CAN Interface (MCMCAN) Table 270 Connections of CAN00 (cont’d) Interface Signals connects Description CAN00:TXD P02.0:ALT(5) CAN transmit output node 0 P12.1:ALT(5) P20.8:ALT(5) P33.8:ALT(5) P33.13:ALT(5) P34.1:ALT(4) Table 271 Connections of CAN01 Interface Signals connects Description CAN01:RXDA from P15.3:IN CAN receive input node 1 CAN01:RXDB from P14.1:IN CAN receive input node 1...
  • Page 420 AURIX™ TC33xEXT CAN Interface (MCMCAN) Table 273 Connections of CAN03 (cont’d) Interface Signals connects Description CAN03:TXD P00.2:ALT(5) CAN transmit output node 3 P11.12:ALT(5) P20.3:ALT(5) P20.10:ALT(5) Note: For the connectivity of the MCMCAN module to the STM module, please refer to the User Manual, chapter MCMCAN User Interface under CAN Transmit Trigger Inputs section.

  • Page 421: Revision History

    AURIX™ TC33xEXT CAN Interface (MCMCAN) 38.5 Revision History Table 274 Revision History Reference Change to Previous Version Comment V1.19.8 First revision of MCMCAN Appendix for TC33xEXT devices. V1.19.9 No changes. V1.19.10 Page 7 Added connections CAN01:RXDE from P14.7 and CAN01:TXD to P14.9. Page 9 Added note at the end of connections tables.

  • Page 422: Flexray™ Protocol Controller (E-Ray)

    AURIX™ TC33xEXT FlexRay™ Protocol Controller (E-Ray) FlexRay™ Protocol Controller (E-Ray) This device doesn’t contain a FlexRay module. User’s Manual 39-1 V2.0.0 FLEXRAY 2021-02 OPEN MARKET VERSION...

  • Page 423: Peripheral Sensor Interface (Psi5)

    AURIX™ TC33xEXT Peripheral Sensor Interface (PSI5) Peripheral Sensor Interface (PSI5) This device doesn’t contain a PSI5. User’s Manual 40-1 V2.0.0 PSI5 2021-02 OPEN MARKET VERSION...

  • Page 424: Peripheral Sensor Interface With Serial Phy Connection (Psi5-S)

    AURIX™ TC33xEXT Peripheral Sensor Interface with Serial PHY Connection (PSI5-S) Peripheral Sensor Interface with Serial PHY Connection (PSI5-S) This device doesn’t contain a PSI5. User’s Manual 41-1 V2.0.0 PSI5-S 2021-02 OPEN MARKET VERSION...

  • Page 425: Gigabit Ethernet Mac (Geth)

    AURIX™ TC33xEXT Gigabit Ethernet MAC (GETH) Gigabit Ethernet MAC (GETH) This document describes the GETH Interface specific appendix for the product TC33xEXT. 42.1 TC33xEXT Specific IP Configuration No product specific configuration for GETH 42.2 TC33xEXT Specific Register Set Register Address Space Table The address space for the module registers is defined in Register Address Space Table.
  • Page 426 AURIX™ TC33xEXT Gigabit Ethernet MAC (GETH) Table 276 Register Overview - GETH (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write GETH_MAC_VLA MAC VLAN Hash Table 0058 U,SV U,SV,P Application N_HASH_TABLE Register Reset Family Spec...
  • Page 427 AURIX™ TC33xEXT Gigabit Ethernet MAC (GETH) Table 276 Register Overview - GETH (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write GETH_MAC_RWK MAC Wake-up Packet Filter 00C4 U,SV U,SV,P Application _PACKET_FILTER Register Reset Family Spec...
  • Page 428 AURIX™ TC33xEXT Gigabit Ethernet MAC (GETH) Table 276 Register Overview - GETH (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write GETH_MAC_HW_ MAC Hardware Feature 0124 U,SV U,SV,P Application FEATURE2 Register 2 Reset Family Spec...
  • Page 429 AURIX™ TC33xEXT Gigabit Ethernet MAC (GETH) Table 276 Register Overview - GETH (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write GETH_MMC_TX_I MMC Transmit Interrupts 0710 U,SV U,SV,P Application NTERRUPT_MAS Mask Register Reset Family Spec...
  • Page 430 AURIX™ TC33xEXT Gigabit Ethernet MAC (GETH) Table 276 Register Overview - GETH (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write GETH_TX_BROA Good And Bad Transmitted 0744 U,SV U,SV,P Application DCAST_PACKETS Broadcast Packets Count Reset Family _GOOD_BAD...
  • Page 431 AURIX™ TC33xEXT Gigabit Ethernet MAC (GETH) Table 276 Register Overview - GETH (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write GETH_RX_PACKE Good And Bad Received 0780 U,SV U,SV,P Application TS_COUNT_GOO Packets Count Register Reset Family D_BAD...
  • Page 432 AURIX™ TC33xEXT Gigabit Ethernet MAC (GETH) Table 276 Register Overview - GETH (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write GETH_RX_256TO Good And Bad 256to511 07B8 U,SV U,SV,P Application 511OCTETS_PAC Octets Packets Received Reset Family KETS_GOOD_BA...
  • Page 433 AURIX™ TC33xEXT Gigabit Ethernet MAC (GETH) Table 276 Register Overview - GETH (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write GETH_TX_LPI_TR Transmitted LPI Transition 07F0 U,SV U,SV,P Application AN_CNTR Count Register Reset Family Spec...
  • Page 434 AURIX™ TC33xEXT Gigabit Ethernet MAC (GETH) Table 276 Register Overview - GETH (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write GETH_RXUDP_E Received UDP Error Packets 0834 U,SV U,SV,P Application RROR_PACKETS Count Register Reset Family Spec...
  • Page 435 AURIX™ TC33xEXT Gigabit Ethernet MAC (GETH) Table 276 Register Overview - GETH (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write GETH_RXUDP_E Received UDP Error Octets 0874 U,SV U,SV,P Application RROR_OCTETS Count Register Reset Family Spec...
  • Page 436 AURIX™ TC33xEXT Gigabit Ethernet MAC (GETH) Table 276 Register Overview - GETH (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write GETH_MAC_TIME MAC Timestamp Status 0B20 U,SV U,SV,P Application STAMP_STATUS Register Reset Family Spec GETH_MAC_TX_T...
  • Page 437 AURIX™ TC33xEXT Gigabit Ethernet MAC (GETH) Table 276 Register Overview - GETH (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write GETH_MAC_PPS MAC PPS 0 Interval Register 0B88 U,SV U,SV,P Application 0_INTERVAL Reset Family Spec...
  • Page 438 AURIX™ TC33xEXT Gigabit Ethernet MAC (GETH) Table 276 Register Overview - GETH (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write GETH_MTL_RXQ MTL Queue 0 Receive 0D3C U,SV U,SV,P Application 0_CONTROL Control Register Reset Family Spec...
  • Page 439 AURIX™ TC33xEXT Gigabit Ethernet MAC (GETH) Table 276 Register Overview - GETH (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write GETH_MTL_RXQi MTL Queue i Receive Missed 0D74 U,SV U,SV,P Application _MISSED_PACKE Packet and Overflow -1)*40 Reset...
  • Page 440 AURIX™ TC33xEXT Gigabit Ethernet MAC (GETH) Table 276 Register Overview - GETH (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write GETH_DMA_CHi_ DMA Channel i Transmit 1120 U,SV U,SV,P Application TXDESC_TAIL_P Descriptor Tail Pointer Reset Family OINTER...
  • Page 441 AURIX™ TC33xEXT Gigabit Ethernet MAC (GETH) Table 276 Register Overview - GETH (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write GETH_DMA_CHi_ DMA Channel i Current 115C U,SV U,SV,P Application CURRENT_APP_R Application Receive Buffer Reset Family XBUFFER...

  • Page 442: Tc33Xext Specific Registers

    AURIX™ TC33xEXT Gigabit Ethernet MAC (GETH) Table 276 Register Overview - GETH (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write GETH_ACCEN1Dx Access Enable Register 1 for 2024 U,SV SV,SE Application (x=0-3) DMAx Reset Family...

  • Page 443: Dma Burst Lengths Limitations By The System

    AURIX™ TC33xEXT Gigabit Ethernet MAC (GETH) Table 277 Connections of GETH (cont’d) Interface Signals connects Description GETH:RXCLKB from P11.4:IN Receive Clock MII and RGMII GETH:RXCLKC from P12.0:IN Receive Clock MII and RGMII GETH:RXD0A from P11.10:IN Receive Data 0 MII, RMII and RGMII (RGMII can use RXD0A only) GETH:RXD1A from P11.9:IN...

  • Page 444: Embedded Fifos

    AURIX™ TC33xEXT Gigabit Ethernet MAC (GETH) 42.7 Embedded FIFOs Each GETH / GETH1 uses two embedded FIFOs. The TX FIFO has a size of 4 kByte, the RX FIFO has a size of 8 kByte. 42.8 Master TAG ID Each module has 4 DMA Channels that share one master interface connecting them to the SRI bus. In order to distinguish the 4 DMAs from each other in the system, the master tag ID will dynamically be changed depending on the currently active DMA.
  • Page 445 AURIX™ TC33xEXT Gigabit Ethernet MAC (GETH) Prior to the application reset the application must switch on (e.g. for f • by configuring CCUCON5.GETHDIV) GETH • Attach an external 125 MHz clock to input GREFCLK • Activate the application reset • Wait for 10 µs Table 280 Clock Lines of Ethernet MAC GETH Clock Line...

  • Page 446: Revision History

    AURIX™ TC33xEXT Gigabit Ethernet MAC (GETH) 42.11 Revision History Table 281 Revision History Reference Change to Previous Version Comment V1.3.10 – Initial version for TC33X V1.3.11 Page 18 Incorrect presentation of registers GETH_MAC_EXT_CONFIGURATION, – GETH_MAC_VERSION and GETH_DMA_MODE removed. V1.3.12 changed to f Page 21 as connection of clk_ptp_ref_i.

  • Page 447: External Bus Unit (Ebu)

    AURIX™ TC33xEXT External Bus Unit (EBU) External Bus Unit (EBU) This device doesn’t contain an EBU module. User’s Manual 43-1 V2.0.0 2021-02 OPEN MARKET VERSION...

  • Page 448: Sd- And Emmc Interface (Sdmmc)

    AURIX™ TC33xEXT SD- and eMMC Interface (SDMMC) SD- and eMMC Interface (SDMMC) This chapter describes the SDMMC. User’s Manual 44-1 V2.0.0 SDMMCV1.0.18 2021-02 OPEN MARKET VERSION...

  • Page 449: Tc33Xext Specific Register Set

    AURIX™ TC33xEXT SD- and eMMC Interface (SDMMC) 44.1 TC33xEXT Specific Register Set Register Address Space Table Table 282 Register Address Space - SDMMC Module Base Address End Address Note SDMMC0 F02B0000 F02B0FFF FPI slave interface Register Overview Table There are no product specific register for this module. 44.2 TC33xEXT Specific Registers There are no product specific register for this module.

  • Page 450: Revision History

    AURIX™ TC33xEXT SD- and eMMC Interface (SDMMC) 44.4 Revision History Table 284 Revision History Reference Change to Previous Version Comment V1.0.17 – No functional changes. V1.0.18 – No functional changes. User’s Manual 44-3 V2.0.0 SDMMCV1.0.18 2021-02 OPEN MARKET VERSION...

  • Page 451: Hardware Security Module (Hsm)

    The HSM is a separate processor subsystem dedicated for security tasks. It is connected as master and slave to the SPB bus. For security reasons this module is described in a separate documentation. Please contact your Infineon representative for further information.

  • Page 452: Input Output Monitor (Iom)

    AURIX™ TC33xEXT Input Output Monitor (IOM) Input Output Monitor (IOM) This device doesn’t contain an IOM. User’s Manual 46-1 V2.0.0 2021-02 OPEN MARKET VERSION...

  • Page 453: 47 8-Bit Standby Controller (Scr)

    AURIX™ TC33xEXT 8-Bit Standby Controller (SCR) 8-Bit Standby Controller (SCR) The description of the SCR for all devices is covered by the family specification. User’s Manual 47-1 V2.0.0 2021-02 OPEN MARKET VERSION...

  • Page 454: Revision History

    AURIX™ TC33xEXT Revision history Document Date of Description of changes version release • Version comparison table updated. V2.0.0 2021-02 • For further changes see respective revision history of each chapter. The version comparison table below gives an overview. • Version comparison table updated. V1.6.0 2020-08 •...
  • Page 455 AURIX™ TC33xEXT Chapter name UM V1.6.0 UM V2.0.0 Content changes chapter version chapter version • SBCU, EBCU V1.2.8 V1.2.9 Yes, see chapter revision history V1.1.20 V1.1.21 No functional changes NVM Subsystem V2.0.7 V2.0.7 • V2.0.11 V2.0.12 No functional changes • V2.0.6 V2.0.6 –...
  • Page 456 AURIX™ TC33xEXT Chapter name UM V1.6.0 UM V2.0.0 Content changes chapter version chapter version MCMCAN V1.19.13 V1.19.13 E-Ray – PSI5 – PSI5-S – GETH V1.3.14 V1.3.15 No functional changes – SDMMC V1.0.18 V1.0.18 – – – User’s Manual RevisionHistory-3 V2.0.0 2021-02 OPEN MARKET VERSION...
  • Page 457 Infineon Technologies, Infineon Technologies in customer's applications. Document reference Infineon Technologies’ products may not be used in The data contained in this document is exclusively any applications where a failure of the product or any intended for technically trained staff. It is the...

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