Subaddress
Register
Bit Description
0xF4
Drive
DR_STR_S[1:0]. Select the drive
Strength
strength for the Sync output signals.
DR_STR_C[1:0]. Select the drive
strength for the Clock output signal.
DR_STR[1:0]. Select the drive
strength for the data output signals.
Can be increased or decreased for
EMC or crosstalk reasons.
Reserved.
0xF8
IF Comp
IFFILTSEL[2:0]. IF filter selection for
Control
Pal and NTSC.
Reserved.
0xF9
VS Mode
EXTEND_VS_MAX_FREQ.
Control
EXTEND_VS_MIN_FREQ.
VS_COAST_MODE[1:0].
Reserved.
Bits
7 6
5
4 3
2
1
0
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
x x
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
0 0
0
0
0
0
1
0
0
0
1
1
0
1
1
0 0
0
0
Rev. B | Page 87 of 100
0
Comments
0
Low drive strength (1x)
1
Medium-low drive
strength (2x)
0
Medium-high drive
strength (3x)
1
High drive strength (4x)
Low drive strength (1x)
Medium-low drive
strength (2x)
Medium-high drive
strength (3x)
High drive strength (4x)
Low drive strength (1x)
Medium-low drive
strength (2x)
Medium-high drive
strength (3x)
High drive strength (4x)
No delay
0
Bypass mode
2 MHz
5 MHz
−3 dB
−2 dB
1
−6 dB
0
+3.5 dB
−10 dB
1
+5 dB
0
Reserved
3 MHz
6 MHz
−2 dB
1
+2 dB
−5 dB
0
+3 dB
−7 dB
1
+5 dB
0
Limit maximum Vsync
frequency to 66.25 Hz
(475 lines/frame)
1
Limit maximum Vsync
frequency to 70.09 Hz
(449 lines/frame)
Limit minimum Vsync
frequency to 42.75 Hz
(731 lines/frame)
Limit minimum Vsync
frequency to 39.51 Hz
(791 lines/frame)
Auto coast mode
50 Hz coast mode
60 Hz coast mode
Reserved
ADV7181B
Notes
0 dB.
NTSC filters.
PAL filters.
This value sets up
the output coast
frequency.
Need help?
Do you have a question about the ADV7181B and is the answer not in the manual?
Questions and answers