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ADV7181B
Table 84. Interrupt Register Map Details
Subaddress
Register
0x40
Interrupt
Config 1
Register
Access
Page 2
0x41
Reserved
0x42
Interrupt
Status 1
Read Only
Register
Access
Page 2
0x43
Interrupt
Clear 1
Write Only
Register
Access
Page 2
Bit Description
INTRQ_OP_SEL[1:0].
Interrupt Drive Level Select.
MPU_STIM_INTRQ[1:0].
Manual Interrupt Set Mode.
Reserved.
MV_INTRQ_SEL[1:0].
Macrovision Interrupt
Select.
INTRQ_DUR_SEL[1:0].
Interrupt Duration Select.
SD_LOCK_Q.
SD_UNLOCK_Q.
Reserved.
Reserved.
Reserved.
SD_FR_CHNG_Q.
MV_PS_CS_Q.
Reserved.
SD_LOCK_CLR.
SD_UNLOCK_CLR.
Reserved.
Reserved.
Reserved.
SD_FR_CHNG_CLR.
MV_PS_CS_CLR.
Reserved.
Bit
7
6
5
4
3
2
1
0
0
1
1
0
1
x
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
x
x
x
x
x
x
x
0
1
x
x
x
0
1
0
1
x
0
1
0
0
0
0
1
0
1
x
Rev. B | Page 68 of 100
0
Comments
0
Open drain
1
Drive low when active
0
Drive high when active
1
Reserved
Manual interrupt mode disabled
Manual interrupt mode enabled
Not used
Reserved
Pseudo sync only
Color stripe only
Pseudo sync or color stripe
3 Xtal periods
15 Xtal periods
63 Xtal periods
Active until cleared
x
0
No change
1
SD input has caused the decoder
to go from an unlocked state to
a locked state
No change
SD input has caused the
decoder to go from a locked
state to an unlocked state
No change
Denotes a change in the free-
run status
No change
Pseudo sync/color striping
detected; see
MV_INTRQ_SEL[1:0],
Macrovision Interrupt
Selection Bits, Address 0x40
(Interrupt Space)[5:4]
for
selection
0
Do not clear
1
Clears SD_LOCK_Q bit
Do not clear
Clears SD_UNLOCK_Q bit
Not used
Not used
Not used
Do not clear
Clears SD_FR_CHNG_Q bit
Do not clear
Clears MV_PS_CS_Q bit
Not used
Notes
These bits
can be
cleared or
masked in
Registers
0x43 and
0x44,
respectively.
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