Analog Devices ADV7181B Manual page 44

ADV7181B
622 623
OUTPUT
VIDEO
H
V
PVBEG[4:0] = 0x5
F
310 311
OUTPUT
VIDEO
H
V
PVBEG[4:0] = 0x5
F
PFTOG[4:0] = 0x3
622 623
OUTPUT
VIDEO
HS
OUTPUT
VS
OUTPUT
FIELD
OUTPUT
310 311
OUTPUT
VIDEO
HS
OUTPUT
VS
OUTPUT
FIELD
OUTPUT
FIELD 1
624 625 1 2 3
PFTOG[4:0] = 0x3
FIELD 2
312 313 314 315 316
Figure 25. PAL Default (BT.656). The Polarity of H, V, and F is Embedded in the Data
FIELD 1
624 1 2 3
625
PVBEG[4:0] = 0x1
FIELD 2
312 313 314 315 316
PVBEG[4:0] = 0x1
Figure 26. PAL Typical Vsync/Field Positions Using Register Writes in Table 56
4 5 6 7
317 318 319 320
4 5 6 7
PVEND[4:0] = 0x4
317 318 319 320
PVEND[4:0] = 0x4
Rev. B | Page 44 of 100
8 9 10 22 23
PVEND[4:0] = 0x4
321 322 335 336 337
PVEND[4:0] = 0x4
8 9 10 11 23
PFTOG[4:0] = 0x6
321 322 323 336 337
PFTOG[4:0] = 0x6
24
24