Changes To Figure 20 - Analog Devices ADV7181B Manual

ADV7181B
PF Polarity FIELD, Address 0x37[3]
The polarity of the FIELD pin can be inverted using the PF bit.
The FIELD pin can be inverted using the PF bit.
525
OUTPUT
VIDEO
H
V
NVBEG[4:0] = 0x5
F
262 263
OUTPUT
VIDEO
H
V
NVBEG[4:0] = 0x5
F
1
APPLIES IF NEWAVMODE = 0:
MUST BE MANUALLY SHIFTED IF NEWAVMODE = 1.
525
OUTPUT
VIDEO
HS
OUTPUT
VS
OUTPUT
FIELD
OUTPUT
262 263
OUTPUT
VIDEO
HS
OUTPUT
VS
OUTPUT
FIELD
OUTPUT
FIELD 1
1 2 3 4 5
NFTOG[4:0] = 0x3
FIELD 2
264 265 266 267 268
NFTOG[4:0] = 0x3
Figure 20. NTSC Default (BT.656). The Polarity of H, V, and F is Embedded in the Data.
FIELD 1
1 2 3 4 5
FIELD 2
264 265 266 267 268
Figure 21. NTSC Typical Vsync/Field Positions Using Register Writes in Table 55
When PF is 0 (default), FIELD is active high.
When PF is 1, FIELD is active low.
6 7 8 9 10
NVEND[4:0] = 0x4
269 270 271 272
NVEND[4:0] = 0x4
6 7 8 9 10
NVBEG[4:0] = 0x0 NVEND[4:0] = 0x3
269 270 271 272 273
NVBEG[4:0] = 0x0 NVEND[4:0] = 0x3
Rev. B | Page 40 of 100
11 12 13 19 20
1
BT.656-4
REG 0x04, BIT 7 = 1
273 274 275 276 283
1
BT.656-4
REG 0x04, BIT 7 = 1
11 12 13 14 15
NFTOG[4:0] = 0x5
274 275 276 277
NFTOG[4:0] = 0x5
21 22
284 285
21 22
284 285