Changes To Table 54 - Analog Devices ADV7181B Manual

Table 55. Recommended User Settings for NTSC (See Figure 21)
Register
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0xE5
0xE6
0xE7
NVBEGDELO NTSC Vsync Begin Delay on Odd Field,
Address 0xE5[7]
When NVBEGDELO is 0 (default), there is no delay.
Setting NVBEGDELO to 1 delays Vsync going high on an odd
field by a line relative to NVBEG.
NVBEGDELE NTSC Vsync Begin Delay on Even Field,
Address 0xE5[6]
When NVBEGDELE is 0 (default), there is no delay.
Setting NVBEGDELE to 1 delays Vsync going high on an even
field by a line relative to NVBEG.
Register Name
Vsync Field Control 1
Vsync Field Control 2
Vsync Field Control 3
Hsync Pos. Control 1
Hsync Pos. Control 1
Hsync Pos. Control 1
Polarity
NTSV_V_Bit_Beg
NTSC_V_Bit_End
NTSC_F_Bit_Tog
1 NVBEGSIGN
ADVANCE BEGIN OF
VSYNC BY NVBEG[4:0]
NOT VALID FOR USER
PROGRAMMING
ODD FIELD?
YES
NVBEGDELO
1 0
ADDITIONAL
DELAY BY
1 LINE
VSBHO
1 0
ADVANCE BY
0.5 LINE
VSYNC BEGIN
Figure 22. NTSC Vsync Begin
Rev. B | Page 41 of 100
0
DELAY BEGIN OF
VSYNC BY NVBEG[4:0]
NO
NVBEGDELE
0 1
ADDITIONAL
DELAY BY
1 LINE
VSBHE
0 1
ADVANCE BY
0.5 LINE
NVBEGSIGN NTSC Vsync Begin Sign, Address 0xE5[5]
Setting NVBEGSIGN to 0 delays the start of Vsync. Set for user
manual programming.
Setting NVBEGSIGN to 1 (default) advances the start of Vsync.
Not recommended for user programming.
NVBEG[4:0] NTSC Vsync Begin, Address 0xE5[4:0]
The default value of NVBEG is 00101, indicating the NTSC
Vsync begin position.
For all NTSC/PAL Vsync timing controls, both the V bit in the
AV code and the Vsync on the VS pin are modified.
ADV7181B
Write
0x1A
0x81
0x84
0x00
0x00
0x7D
0xA1
0x41
0x84
0x06