DIGITAL-LOGIC MICROSPACE MSM800SEV Technical User's Manual page 80

DIGITAL-LOGIC AG
PRE2ACT: Pre to ACT period (tRP). Minimum number of SDROM clocks between PRE and
ACT commands
ACT2CMD: Delay time from ACT to Read/Write (tRCD). Minimum number of SDRAM clocks
between ACT and Read/Write Commands
ACT2ACT: ACT(0) to ACT(1) Period (tRRD). Minimum number of SDRAM clocks between
ACT and ACT commands to two different component banks within the same module bank.
REF2ACT: Refresh to Activity Delay (tRFC). Minimum number of SDCLKS 90-31) between
refresh and next command, usually an activate
System Clock/PLL and Clock Gating Configuration
The system clock/PLL allows the setting of the clocks for the AMD GeodeTM system.
Clock Mode: Allows the clock speed to either be determined by the hardware strapping or manual settings.
If the H/W strapping option is selected, then the manual divisor settings will be grayed out.
Manual divisor settings
Mdiv: Options from 2 to 17
Vdiv: Options from 2 to 9
FbDiv: Options from 6 to 61
The formula for the Mdiv, VDiv, and FbDiv is as follows
(PCI*FbDiv)/VDiv = CPU speed and (PCI*FbDiv)/MDiv = GeodeLinkTM speed.
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MSM800 SEV Manual V1.0A