DIGITAL-LOGIC MICROSPACE MSM800SEV Technical User's Manual page 36

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CMOS Map
Continued...
Location Description
Byte 3
28h
bits 7-6 = Reserved
bits 5-0 = Upper 6 Bits of Write Precompensation
Byte 4
29h
bits 7-0 = Number of Heads
Byte 5
2Ah
bits 7-0 = Sectors Per Track
2Bh Boot Password
bit 7
bits 6-0 = Calculated Password
2Ch SCU Password
bit 7
bits 6-0 = Calculated Password
2Dh Reserved
2Eh High Byte of Checksum - Locations 10h to 2Dh
2Fh Low Byte of Checksum - Locations 10h to 2Dh
30h Extended RAM (KB) detected by POST - Low Byte
31h Extended RAM (KB) detected by POST - High Byte
32h BCD Value for Century
33h Base Memory Installed
bit 7
bits 6-0 = Reserved
34h
Minor CPU Revision
Differentiates CPUs within a CPU type (i.e., 486SX vs 486 DX,
vs 486 DX/2). This is crucial for correctly determining CPU
input clock frequency. During a power on reset, Reg DL holds
minor CPU revision.
35h
Major CPU Revision
Differentiates between different CPUs (i.e., 386, 486, Pentium).
This is crucial for correctly determining CPU input clock fre-
quency. During a power on reset, Reg DH holds major CPU
revision.
36h Hotkey Usage
bits 7-6 = Reserved
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
40h-7Fh Definitions for these locations vary depending on the chipset.
= Enable/Disable Password
0 =
1 =
= Enable/Disable Password
0 =
1 =
= Flag for Memory Size
0 =
1 =
= Semaphore for Completed POST
= Semaphore for 0 Volt POST
= Semaphore for already in SCU menu
= Semaphore for already in PM menu
= Semaphore for SCU menu call pending
= Semaphore for PM menu call pending
Disable Password
Enable Password
Disable Password
Enable Password
640KB
512KB
(not currently used)
36
MSM800 SEV Manual V1.0A