System Architecture - Analog Devices EZ-KIT Lite ADSP-BF538F System Manual

System Architecture

System Architecture
This section describes the processor's configuration on the EZ-KIT Lite
board.
JTAG
Conn
CAN
Transceiver
RS-232
RS-232
Female Interface
Power
Regulation
Figure 2-1. System Architecture
This EZ-KIT Lite is designed to demonstrate capabilities of the
ADSP-BF538F Blackfin processor. The processor has an IO voltage of
3.3V. The core voltage of the processor is supplied by the internal voltage
regulator.
2-2
25 MHz
Oscillator
32.768 KHz
Oscillator
RTC
ADSP-BF538F
UARTs SPORTs
(3) (4)
UART SPORT
Conns Conns
ADSP-BF538F EZ-KIT Lite Evaluation System Manual
64 MB 4 MB
SDRAM Flash
(32M x 16) (2M x 16 )
EBUI
DSP
SPIs PPI GPIO
ADC/
DAC
(3)
PPI Stereo
SPI
Conn In/Out
Conns
Expansion
Connectors
(3)
PBs (4)
LEDs (6)
ELVIS