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Jumper and Switch Settings
FCE Enable Switch (SW14)
The flash chip enable (FCE) switch (
nect to the internal flash memory. Since the internal memory is 1 MB,
only one
signal must be connected at a time. For each switch listed in
~AMS
Table 2-7
that is turned
by 1 MB.
Table 2-7. FCE Enable Switch (SW14)
Processor Signal
~AMS0
~AMS1
~AMS2
~AMS3
Audio Enable Switch (SW7)
The audio enable switch (
cessor (positions 1–5) and determines how the clock for the audio circuit
generates and connects (positions 6–8). Position 8 determines if the ADC
is in master or slave mode. When in master mode (position 8 is
ADC generates the clock. When in slave mode (position 8 is
cessor generates the clock. Positions 6 and 7 connect together the transmit
and receive clocks (see
Table 2-8. Audio Enable Switch (SW7)
EZ-KIT Lite Signal
DR0PRI
RSCLK0
RFS0
2-12
, the size of available flash memory is reduced
ON
SW14 Switch Position (Default)
1 (
)
OFF
2 (
)
OFF
3 (
)
OFF
4 (
)
OFF
) disconnects the audio signals from the pro-
SW7
Table
2-8).
SW7 Switch Position (Default)
1 (
)
ON
2 (
)
ON
3 (
)
ON
ADSP-BF538F EZ-KIT Lite Evaluation System Manual
) selects which
SW14
Processor Signal
DR0PRI
RSCLK0
RFS0
signals con-
~AMS
), the
ON
), the pro-
OFF
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