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Table 51. Supported NVDIMM-N for quad processor configurations (continued)
Configuration
Configuration 9
Configuration 10
Configuration 11
Configuration 12
Configuration 13
Configuration 14
Configuration 15
DCPMM installation guidelines
The following are the recommended guidelines for installing data center persistent memory module (DCPMM) memory modules:
•
Each system supports maximum of one DCPMM memory module per channel.
NOTE:
If two different DCPMM capacities are mixed, an F1/F2 warning is displayed as the configuration is not
supported.
•
DCPMM can be mixed with RDIMM, LRDIMM, and 3DS LRDIMM.
120
Installing and removing system components
Description
44x 32 GB RDIMMs, 4x
NVDIMM-Ns
24x 16 GB RDIMMs, 6x
NVDIMM-Ns
24x 32 GB RDIMMs, 6x
NVDIMM-Ns
42x 32 GB RDIMMs, 6x
NVDIMM-Ns
24x 16 GB RDIMMs, 12x
NVDIMM-Ns
24x 32 GB RDIMMs, 12x
NVDIMM-Ns
36x 32 GB RDIMMs, 12x
NVDIMM-Ns
Memory population rules
RDIMMs
Processor1 {A1, 2, 3, 4, 5, 6, 7,
8, 9, 10},
Processor2 {B1, 2, 3, 4, 5, 6, 7,
8, 9, 10},
Processor3 {C1, 2, 3, 4, 5, 6, 7,
8, 9, 10, 11, 12}
Processor4 {D1, 2, 3, 4, 5, 6, 7,
8, 9, 10, 11, 12}
Processor1 {A1, 2, 3, 4, 5, 6},
Processor2 {B1, 2, 3, 4, 5, 6}
Processor3 {C1, 2, 3, 4, 5, 6}
Processor4 {D1, 2, 3, 4, 5, 6}
Processor1 {A1, 2, 3, 4, 5, 6},
Processor2 {B1, 2, 3, 4, 5, 6},
Processor3 {C1, 2, 3, 4, 5, 6}
Processor4 {D1, 2, 3, 4, 5, 6}
Processor1 {A1, 2, 3, 4, 5, 6, 7,
8, 9},
Processor2 {B1, 2, 3, 4, 5, 6, 7,
8, 9}
Processor3 {C1, 2, 3, 4, 5, 6, 7,
8, 9, 10, 11, 12}
Processor4 {D1, 2, 3, 4, 5, 6, 7,
8, 9, 10, 11, 12}
Processor1 {A1, 2, 3, 4, 5, 6},
Processor2 {B1, 2, 3, 4, 5, 6},
Processor3 {C1, 2, 3, 4, 5, 6}
Processor4 {D1, 2, 3, 4, 5, 6}
Processor1 {A1, 2, 3, 4, 5, 6},
Processor2 {B1, 2, 3, 4, 5, 6},
Processor3 {C1, 2, 3, 4, 5, 6}
Processor4 {D1, 2, 3, 4, 5, 6}
Processor1 {A1, 2, 3, 4, 5, 6},
Processor2 {B1, 2, 3, 4, 5, 6},
Processor3 {C1, 2, 3, 4, 5, 6, 7,
8, 9, 10, 11, 12}
Processor 4 {D1, 2, 3, 4, 5, 6, 7,
8, 9, 10, 11, 12}
NVDIMM-N
Processor1 {A11, 12},
Processor2 {B11, 12}
Processor1 {A7, 8, 9}
Processor2 {B7, 8, 9}
Processor1 {A7, 8, 9}
Processor2 {B7, 8, 9}
Processor1 {A10,11,12}
Processor2 {B10, 11, 12}
Processor1 {A7, 8, 9, 10, 11, 12},
Processor2 {B7, 8, 9, 10, 11, 12}
Processor1 {A7, 8, 9, 10, 11, 12},
Processor2 {B7, 8, 9, 10, 11, 12}
Processor1 {A7, 8, 9, 10, 11, 12},
Processor2 {B7, 8, 9, 10, 11, 12}
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