Texas Instruments CC3235 SimpleLink Series Technical Reference Manual page 8

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13.6.3 Basic APIs for Enabling and Configuring the Interface
13.6.4 APIs for Data Transfer [Direct Access to FIFO and DMA Setup]
13.6.5 APIs for Interrupt Usage
13.6.6 APIs for Setting Up ADC Timer for Time-Stamping the Samples
14
Parallel Camera Interface Module
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14.1
Overview
14.2
Image Sensor Interface
14.3
Functional Description
14.3.1 Modes of Operation
14.3.2 FIFO Buffer
14.3.3 Reset
14.3.4 Clock Generation
14.3.5 Interrupt Generation
14.3.6 DMA Interface
14.4
Programming Model
14.4.1 Camera Core Reset
14.4.2 Enable the Picture Acquisition
14.4.3 Disable the Picture Acquisition
14.5
Interrupt Handling
14.5.1 FIFO_OF_IRQ (FIFO Overflow)
14.5.2 FIFO_UF_IRQ (FIFO Underflow)
14.6
Camera Registers
14.6.1 CC_SYSCONFIG Register (Offset = 10h) [reset = 0h]
14.6.2 CC_SYSSTATUS Register (Offset = 14h) [reset = X]
14.6.3 CC_IRQSTATUS Register (Offset = 18h) [reset = 0h]
14.6.4 CC_IRQENABLE Register (Offset = 1Ch) [reset = 0h]
14.6.5 CC_CTRL Register (Offset = 40h) [reset = 1001h]
14.6.6 CC_CTRL_DMA Register (Offset = 44h) [reset = 207h]
14.6.7 CC_CTRL_XCLK Register (Offset = 48h) [reset = 0h]
14.6.8 CC_FIFODATA Register (Offset = 4Ch) [reset = X]
14.7
Peripheral Library APIs
14.8
Developer's Guide
14.8.1 Using Peripheral Driver APIs for Capturing an Image
14.8.2 Using Peripheral Driver APIs for Communicating With Image Sensors
15
Power, Reset, and Clock Management
...................................................................................................................
15.1
Overview
15.1.1 Power Management Unit (PMU)
15.1.2 VBAT Wide-Voltage Connection
15.1.3 Supply Brownout and Blackout
15.1.4 Application Processor Power Modes
15.2
Power Management Control Architecture
15.2.1 Global Power-Reset-Clock Manager (GPRCM)
15.2.2 Application Reset-Clock Manager (ARCM)
................................................................................................................
15.3
PRCM APIs
15.3.1 MCU Initialization
15.3.2 Reset Control
15.3.3 Peripheral Reset
15.3.4 Reset Cause
15.3.5 Clock Control
15.3.6 Low-Power Modes
15.3.7 Sleep (SLEEP)
15.3.8 Low-Power Deep Sleep (LPDS)
15.3.9 Hibernate (HIB)
8
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Copyright © 2019, Texas Instruments Incorporated
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www.ti.com
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SWRU543 – January 2019
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