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Texas Instruments CC3235 SimpleLink Series Technical Reference Manual

Texas Instruments CC3235 SimpleLink Series Technical Reference Manual

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CC3235x SimpleLink

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Technical Reference Manual

Literature Number: SWRU543

January 2019

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Page 1 ™ ® CC3235x SimpleLink Wi-Fi Internet of Things Technical Reference Manual Literature Number: SWRU543 January 2019...
Page 2 ........................Overview ..................... Functional Description ..................3.2.1 System Timer (SysTick) ..............3.2.2 Nested Vectored Interrupt Controller (NVIC) ..................3.2.3 System Control Block (SCB) ........................ Register Map Contents SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 3 UARTLCRH Register (Offset = 2Ch) [reset = 0h] ............6.3.7 UARTCTL Register (Offset = 30h) [reset = 300h] ............6.3.8 UARTIFLS Register (Offset = 34h) [reset = 12h] SWRU543 – January 2019 Contents Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 4 SPI (Serial Peripheral Interface) ........................Overview ......................8.1.1 Features ....................Functional Description ........................ 8.2.1 ....................8.2.2 SPI Transmission ..................... 8.2.3 Master Mode ....................... 8.2.4 Slave Mode Contents SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 5 9.5.12 GPTMTBMATCHR Register (offset = 34h) [reset = FFFFh] ............9.5.13 GPTMTAPR Register (offset = 38h) [reset = 0h] ............9.5.14 GPTMTBPR Register (offset = 3Ch) [reset = 0h] SWRU543 – January 2019 Contents Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 6 11.7.14 MMCHS_STAT Register (Offset = 230h) [reset = 0h] ............11.7.15 MMCHS_IE Register (Offset = 234h) [reset = 0h] ............11.7.16 MMCHS_ISE Register (Offset = 238h) [reset = 0h] Contents SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 7 13.4.1 ADC Register Description ..................13.5 Initialization and Configuration ................13.6 Peripheral Library APIs for ADC Operation ......................13.6.1 Overview ................13.6.2 Configuring the ADC Channels SWRU543 – January 2019 Contents Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 8 ..................... 15.3.4 Reset Cause ....................15.3.5 Clock Control ....................15.3.6 Low-Power Modes ....................15.3.7 Sleep (SLEEP) ................15.3.8 Low-Power Deep Sleep (LPDS) ....................15.3.9 Hibernate (HIB) Contents SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 9 15.6.47 SLPTMRCFG Register (offset = 114h) [reset = 0h] ............15.6.48 WAKENWP Register (offset = 118h) [reset = 0h] ............. 15.6.49 RCM_IS Register (offset = 120h) [reset = 0h] SWRU543 – January 2019 Contents Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 10 17.4.22 AES_C_LENGTH_0 Register (Offset = 54h) [reset = 0h] ..........17.4.23 AES_C_LENGTH_1 Register (Offset = 58h) [reset = X] ..........17.4.24 AES_AUTH_LENGTH Register (Offset = 5Ch) [reset = 0h] Contents SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 11 18.5.18 DES_IRQSTATUS Register (Offset = 103Ch) [reset = 0h] ..........18.5.19 DES_IRQENABLE Register (Offset = 1040h) [reset = 0h] ......................SHA/MD5 Accelerator ..................19.1 SHA/MD5 Functional Description ..................19.1.1 SHA/MD5 Block Diagram SWRU543 – January 2019 Contents Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 12 20.1.1 CRC Support ..................20.2 Initialization and Configuration ................. 20.2.1 CRC Initialization and Configuration ......................20.3 CRC Registers ............20.3.1 CRCCTRL Register (Offset = C00h) [reset = 0h] Contents SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 13 DMA_MIS Register (offset = A0h) [reset = 0h] ................ DMA_RIS Register (offset = A4h) [reset = 0h] ..............GPTTRIGSEL Register (offset = B0h) [reset = 0h] SWRU543 – January 2019 Contents Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 14: Table Of Contents
....................4-10. DMA_ALTBASE Register ....................4-11. DMA_WAITSTAT Register ....................4-12. DMA_SWREQ Register ..................4-13. DMA_USEBURSTSET Register ..................4-14. DMA_USEBURSTCLR Register ..................4-15. DMA_REQMASKSET Register List of Figures SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 15 Complete Data Transfer With a 7-Bit Address ....................... 7-5. R/S Bit in First Byte ..............7-6. Data Validity During Bit Transfer on the I2C Bus ....................7-7. Master Single TRANSMIT SWRU543 – January 2019 List of Figures Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 16 8-14. Flow Chart – Module Initialization ................8-15. Flow Chart – Common Transfer Sequence ............8-16. Flow Chart – Transmit and Receive (Master and Slave) List of Figures SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 17 10-5. WDTICR Register ......................10-6. WDTRIS Register ...................... 10-7. WDTTEST Register ...................... 10-8. WDTLOCK Register ....................10-9. Watchdog Flow Chart ................10-10. System Watchdog Recovery Sequence SWRU543 – January 2019 List of Figures Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 18 ......................12-27. XSTAT Register ......................12-28. XSLOT Register ....................... 12-29. XEVTCTL Register ......................12-30. SRCTLn Registers ......................12-31. XBUFn Registers ......................12-32. RBUFn Registers List of Figures SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 19 ....................15-5. CAMCLKEN Register ....................15-6. CAMSWRST Register ....................15-7. MCASPCLKEN Register ....................15-8. MCASPSWRST Register ....................15-9. SDIOMCLKCFG Register ....................15-10. SDIOMCLKEN Register SWRU543 – January 2019 List of Figures Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 20 16-3. I/O Pad Data and Control Path Architecture in CC32xx ..................16-4. Wake on Pad for Hibernate Mode ...................... 17-1. AES Block Diagram ..................... 17-2. AES - ECB Feedback Mode List of Figures SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 21 ....................17-46. AES_REVISION Register ..................... 17-47. AES_SYSCONFIG Register ..................... 17-48. AES_IRQSTATUS Register ..................... 17-49. AES_IRQENABLE Register ....................17-50. CRYPTOCLKEN Register ....................17-51. DTHE_AES_IM Register SWRU543 – January 2019 List of Figures Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 22 ..................19-14. SHAMD5_IDIGEST_B Register ..................19-15. SHAMD5_IDIGEST_C Register ..................19-16. SHAMD5_IDIGEST_D Register ..................19-17. SHAMD5_IDIGEST_E Register ..................19-18. SHAMD5_IDIGEST_F Register ..................19-19. SHAMD5_IDIGEST_G Register List of Figures SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 23 21-13. On-Chip Flash Programming and Update ....................21-14. Flash Debug Image Layout ....................... B-1. DMA_IMR Register ....................... B-2. DMA_IMS Register ....................... B-3. DMA_IMC Register ....................... B-4. DMA_ICR Register SWRU543 – January 2019 List of Figures Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 24 ....................... B-5. DMA_MIS Register ....................... B-6. DMA_RIS Register ....................B-7. GPTTRIGSEL Register List of Figures SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 25 µDMA Register Map ......................4-6. DM Registers ................ 4-7. DMA_SRCENDP Register Field Descriptions ................. 4-8. DMA_DSTENDP Register Field Descriptions ................4-9. DMA_CHCTL Register Field Descriptions SWRU543 – January 2019 List of Tables Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 26 ................6-8. UARTLCRH Register Field Descriptions ................. 6-9. UARTCTL Register Field Descriptions ................6-10. UARTIFLS Register Field Descriptions ................... 6-11. UARTIM Register Field Descriptions List of Tables SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 27 ..............8-11. SPI_MODULCTRL Register Field Descriptions ................8-12. SPI_CHCONF Register Field Descriptions ................8-13. SPI_CHSTAT Register Field Descriptions ................8-14. SPI_CHCTRL Register Field Descriptions SWRU543 – January 2019 List of Tables Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 28 ................11-6. MMCHS_CON Register Field Descriptions ................11-7. MMCHS_BLK Register Field Descriptions ................11-8. MMCHS_ARG Register Field Descriptions ................11-9. MMCHS_CMD Register Field Descriptions List of Tables SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 29 12-34. RBUFn Register Field Descriptions ......................13-1. ADC Registers ....................13-2. ADC_MODULE Registers ................13-3. ADC_CTRL Register Field Descriptions ..............13-4. ADC_CH0_IRQ_EN Register Field Descriptions SWRU543 – January 2019 List of Tables Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 30 ................15-14. APSPISWRST Register Field Descriptions ................15-15. DMACLKEN Register Field Descriptions ................15-16. DMASWRST Register Field Descriptions ................15-17. GPIO0CLKEN Register Field Descriptions List of Tables SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 31 16-10. Pin Groups for SD-Card Interface .................... 16-11. Pad Configuration Registers ........16-12. GPIO_PAD_CONFIG_0 to GPIO_PAD_CONFIG_32 Register Description ..............16-13. Recommended Pin Multiplexing Configurations SWRU543 – January 2019 List of Tables Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 32 17-44. DTHE_AES_IC Register Field Descriptions ......................18-1. Key Repartition ....................18-2. DES Global Initialization ..................18-3. DES Algorithm Type Configuration ................... 18-4. 3DES Algorithm Type Configuration List of Tables SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 33 ..............19-24. SHAMD5_IDIGEST_E Register Field Descriptions ..............19-25. SHAMD5_IDIGEST_F Register Field Descriptions ..............19-26. SHAMD5_IDIGEST_G Register Field Descriptions ..............19-27. SHAMD5_IDIGEST_H Register Field Descriptions SWRU543 – January 2019 List of Tables Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 34 ................. B-2. DMA_IMR Register Field Descriptions ................. B-3. DMA_IMS Register Field Descriptions ................. B-4. DMA_IMC Register Field Descriptions ................. B-5. DMA_ICR Register Field Descriptions List of Tables SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 35 ................. B-6. DMA_MIS Register Field Descriptions ................. B-7. DMA_RIS Register Field Descriptions ................B-8. GPTTRIGSEL Register Field Descriptions SWRU543 – January 2019 List of Tables Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 36: Register Bit Accessibility And Initial Condition
Condition after POR -[0], -[1] Condition after BOR -{0},-{1} Condition after Brownout Glossary TI Glossary — This glossary lists and explains terms, acronyms, and definitions. Read This First SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 37 TI Embedded Processors Wiki— Texas Instruments Embedded Processors Wiki. Established to help developers get started with Embedded Processors from Texas Instruments and to foster innovation and growth of general knowledge about the hardware and software surrounding these devices. TI Product Information Centers (PIC)—...
Page 38 Bluetooth is a registered trademark of Bluetooth SIG, Inc.. Wi-Fi, Wi-Fi Direct are registered trademarks of Wi-Fi Alliance. SimpleLink, Texas Instruments, E2E, Internet-on-a chip, are trademarks of ~ Texas Instruments. is a registered trademark of ~ARM Ltd. Wi-Fi, Wi-Fi Direct, are registered trademarks of ~Wi-Fi Alliance.
Page 39 Chapter 1 SWRU543 – January 2019 Architecture Overview ........................... Topic Page ....................... Introduction ..................Architecture Overview ................... Functional Overview SWRU543 – January 2019 Architecture Overview Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 40 The device also supports WPA2 personal and enterprise security and WPS 2.0. The Wi-Fi Internet-on-a chip™ includes embedded TCP/IP and TLS/SSL stacks, HTTP server, and multiple Internet protocols. Architecture Overview SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 41: Cc32Xx Mcu And Wi-Fi
32 KHz RC OSC Supply Monitor 1.85 V Regulated Wake Up Sequencer 32 KHx XOSC DIG DCDC ANA DCDC PA DCDC nRESET 32.765 XTAL Complete Chip Reset SWRU543 – January 2019 Architecture Overview Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 42 A high-speed alarm timer using the system clock • A simple counter used to measure time to completion and time used • An internal clock-source control based on missing or meeting durations Architecture Overview SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 43 The CC32xx DriverLib is a software library that controls on-chip peripherals. The library performs both peripheral initialization and control functions, with a choice of polled or interrupt-driven peripheral support. SWRU543 – January 2019 Architecture Overview Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 44 Source and destination address increment size of byte, halfword, word, or no increment • Maskable peripheral requests • Interrupt on transfer completion, with a separate interrupt per channel Architecture Overview SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 45 Programmable clock and frame-sync polarity (rising or falling edge) • Programmable word length (bits per word): 16 and 24 bits • Programmable fractional divider for bit-clock generation, up to 9 MHz SWRU543 – January 2019 Architecture Overview Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 46 FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8 • Standard asynchronous communication bits for start, stop, and parity • Line-break generation and detection Architecture Overview SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 47 1.3.12 SD Card Host The CC32xx includes an SD-Host interface for applications that require mass storage. The SD-Host interface support is currently limited to 1-bit mode. SWRU543 – January 2019 Architecture Overview Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 48 – Complete system recovery from any scenario at which the scenario is stuck can be achieved by using a combination of WDT reset and hibernate sleep. Architecture Overview SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 49 Automatic output isolation during reset and hibernate • Configurable pullup and pulldown (10 µA nominal) • Software-configurable pad state retention during LPDS • All digital I/Os are nonfail-safe SWRU543 – January 2019 Architecture Overview Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 50 Chapter 2 SWRU543 – January 2019 ® Cortex -M4 Processor ........................... Topic Page ......................Overview ..................Functional Description ® SWRU543 – January 2019 Cortex -M4 Processor Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 51 Processor Technical Reference Manual (ARM 100166_0001_00). ® For technical details on the instruction set, see the Cortex -M4 Devices Generic User Guide (ARM DUI 0553A). SWRU543 – January 2019 ® Cortex -M4 Processor Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 52: Application Cpu Block Diagram
SRAM architecture, this type of patching is no longer required. ® For more information on the Cortex -M4 debug capabilities, see the Arm Debug Interface V5 Architecture Specification. ® SWRU543 – January 2019 Cortex -M4 Processor Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 53: Tpiu Block Diagram
System Control Block (SCB): The programming model interface to the processor. The SCB provides system implementation information and system control, including configuration, control, and reporting of system exceptions (see System Control Block [SCB] in Section 3.2.3). SWRU543 – January 2019 ® Cortex -M4 Processor Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 54: Summary Of Processor Mode, Privilege Level, And Stack Use
Applications Privileged or unprivileged Main stack or process stack Handler Exception handlers Always privileged Main stack See the CONTROL register in Section 2.2.2.2.8. ® SWRU543 – January 2019 Cortex -M4 Processor Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 55: Cortex -M4 Register Set
Cortex General-Purpose register 9 – – Cortex General-Purpose register 10 – – Cortex General-Purpose register 11 – – Cortex General-Purpose register 12 – – Stack pointer SWRU543 – January 2019 ® Cortex -M4 Processor Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 56 THUMB bit of the EPSR at reset and must be 1. The PC register can be accessed in either privileged or unprivileged mode. ® SWRU543 – January 2019 Cortex -M4 Processor Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 57: Psr Register Combinations
FAULTMASK register. See the Cortex -M4 Devices Generic User Guide (ARM DUI 0553A) for more information on these instructions. SWRU543 – January 2019 ® Cortex -M4 Processor Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 58 Within the memory map, attempts to read or write addresses in reserved spaces result in a bus fault. In addition, attempts to write addresses in the flash range also result in a bus fault. ® SWRU543 – January 2019 Cortex -M4 Processor Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 59: Memory Map
Flash patch and breakpoint (FPB) 0xE000.E000 0xE000.EFFF Cortex-M4 peripherals (NVIC, SysTick,SCB) 0xE004.0000 0xE004.0FFF Trace port interface unit (TPIU) 0xE004.1000 0xE004.1FFF Reserved for embedded trace macrocell (ETM) SWRU543 – January 2019 ® Cortex -M4 Processor Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 60: Sram Memory Bit-Banding Regions
Directly Accessing a Bit-Band Region Behavior of memory accesses describes the behavior of direct byte, halfword, or word accesses to the bit- band regions. ® SWRU543 – January 2019 Cortex -M4 Processor Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 61: Data Storage
Step 1 might be out of date. The software must retry the entire read-modify-write sequence. SWRU543 – January 2019 ® Cortex -M4 Processor Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 62 In this case, both exceptions are in the active state. • Active and Pending: The exception is being serviced by the processor, and there is a pending ® SWRU543 – January 2019 Cortex -M4 Processor Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 63 SYSHNDCTRL register and the DIS0 register). For more information about hard faults, memory management faults, bus faults, and usage faults, see Section 2.2.5. SWRU543 – January 2019 ® Cortex -M4 Processor Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 64: Exception Types
16- or 32-Bit Timer A1A 0x0000.0098 16- or 32-Bit Timer A1B 0x0000.009C 16- or 32-Bit Timer A2A 0x0000.00A0 16- or 32-Bit Timer A2B ® SWRU543 – January 2019 Cortex -M4 Processor Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 65 0x0000 0400 to 0x3FFF FC00. When configuring the VTABLE register, the offset must be aligned on a 1024-byte boundary. SWRU543 – January 2019 ® Cortex -M4 Processor Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 66: Vector Table
For example, if both IRQ[0] and IRQ[1] are pending and have the same priority, then IRQ[0] is processed before IRQ[1]. ® SWRU543 – January 2019 Cortex -M4 Processor Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 67 ® Figure 2-6 shows the Cortex -M4 stack frame layout, which is similar to that of Armv7-M implementations without an FPU. SWRU543 – January 2019 ® Cortex -M4 Processor Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 68: Exception Stack Frame
Default memory mismatch on Memory management fault Memory Management Fault Status MSTKE exception stacking (MFAULTSTAT) Occurs on an access to an XN region. ® SWRU543 – January 2019 Cortex -M4 Processor Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 69 Usage Fault Status (UFAULTSTAT) DIV0 Attempting to use an instruction set other than the Thumb instruction set, or returning to a nonload-store-multiple instruction with ICI continuation. SWRU543 – January 2019 ® Cortex -M4 Processor Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 70: Fault Status And Fault Address Registers
When the processor is in the lockup state, it does not execute any instructions. The processor remains in lockup state until it is reset, an NMI occurs, or it is halted by a debugger. ® SWRU543 – January 2019 Cortex -M4 Processor Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 71 AHB interconnect, fast execution and retention over the entire range of zero wait-state SRAM. • SLEEP: Sleep mode stops the processor clock (clock gating). SWRU543 – January 2019 ® Cortex -M4 Processor Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 72: Power-Management Architecture In Cc32Xx Soc
32.768 KHz SW Register I/F LF-XOSC 40 MHz HF-XOSC SRAM External (Boot, Drivers) (Code, Data) SPI Flash 240 MHz I/O Mux I/O Pads ® SWRU543 – January 2019 Cortex -M4 Processor Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 73 Rt, [Rn, #offset] Load register exclusive – LDREXB Rt, [Rn] Load register exclusive with byte – LDREXH Rt, [Rn] Load register exclusive with halfword – SWRU543 – January 2019 ® Cortex -M4 Processor Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 74 {Rd,} Rn, Rm Signed divide – {Rd,} Rn, Rm Select bytes – – Send event – SHADD16 {Rd,} Rn, Rm Signed halving add 16 – ® SWRU543 – January 2019 Cortex -M4 Processor Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 75 {Rd,} Rn, Rm,{,ROR #} Dual extend 8 bits to 16 and add – SXTAH {Rd,} Rn, Rm,{,ROR #} Extend 16 bits to 32 and add – SWRU543 – January 2019 ® Cortex -M4 Processor Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 76 Unsigned extend byte 16 – UXTH {Rd,} Rm, {,ROR #n} Zero extend a halfword – – Wait for event – – Wait for interrupt – ® SWRU543 – January 2019 Cortex -M4 Processor Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 77 Chapter 3 SWRU543 – January 2019 ® Cortex -M4 Peripherals ........................... Topic Page ......................Overview ..................Functional Description ..................... Register Map SWRU543 – January 2019 ® Cortex -M4 Peripherals Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 78: Core Peripheral Register Regions
The SysTick counter runs on the system clock. If this clock signal is stopped for low-power mode, the SysTick counter stops. Ensure software uses aligned word accesses to access the SysTick registers. ® SWRU543 – January 2019 Cortex -M4 Peripherals Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 79 Software writes to the corresponding interrupt set-pending register bit, or to the Software Trigger Interrupt (SWTRIG) register to make a software-generated interrupt pending. See the INT bit in the PEND0 register or SWTRIG register. SWRU543 – January 2019 ® Cortex -M4 Peripherals Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 80: Peripherals Register Map
Interrupt 64 to 95 Clear Enable 0x18C DIS3 0x0000.0000 Interrupt 96 to 127 Clear Enable 0x190 DIS4 0x0000.0000 Interrupt 128 to 159 Clear Enable ® SWRU543 – January 2019 Cortex -M4 Peripherals Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 81 PRI21 0x0000.0000 Interrupt 84 to 87 Priority 0x458 PRI22 0x0000.0000 Interrupt 88 to 91 Priority 0x45C PRI23 0x0000.0000 Interrupt 92 to 95 Priority SWRU543 – January 2019 ® Cortex -M4 Peripherals Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 82: Faults
Configurable Fault Status 0xD2C HFAULTSTAT R/W1C 0x0000.0000 Hard Fault Status 0xD34 MMADDR – Memory Management Fault Address 0xD38 FAULTADDR – Bus Fault Address ® SWRU543 – January 2019 Cortex -M4 Peripherals Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 83: Cortex ® -M4 Instruction Summary
Section 3.3.1.21 D2Ch HFAULTSTAT Hard Fault Status Section 3.3.1.22 D38h FAULTDDR Bus Fault Address Section 3.3.1.23 F00h SWTRIG Software Trigger Interrupt Section 3.3.1.24 SWRU543 – January 2019 ® Cortex -M4 Peripherals Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 84: Actlr Register
However, IT folding can cause jitter in looping. If a task must avoid jitter, set the DISFOLD bit before executing the task, to disable IT folding. 0h = No effect. 1h = Disables IT folding. ® SWRU543 – January 2019 Cortex -M4 Peripherals Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 85 0h = No effect. 1h = Disables interruption of load multiple and store multiple instructions. SWRU543 – January 2019 ® Cortex -M4 Peripherals Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 86: Stctrl Register
0, the COUNT bit is set and an interrupt is generated if enabled by INTEN. The counter then loads the RELOAD value again and begins counting. ® SWRU543 – January 2019 Cortex -M4 Peripherals Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 87: Streload Register
Reset Description 31-24 RESERVED 23-0 RELOAD Reload Value Value to load into the SysTick Current Value (STCURRENT) register when the counter reaches 0. SWRU543 – January 2019 ® Cortex -M4 Peripherals Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 88: Stcurrent Register
This register is write-clear. Writing to it with any value clears the register. Clearing this register also clears the COUNT bit of the STCTRL register. ® SWRU543 – January 2019 Cortex -M4 Peripherals Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 89: 0 To En_6 Register
0h (R) = On a read, indicates the interrupt is disabled. 1h (W) = On a write, enables the interrupt. 1h (R) = On a read, indicates the interrupt is enabled. SWRU543 – January 2019 ® Cortex -M4 Peripherals Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 90: Dis_0 To Dis_6 Register
0h (R) = On a read, indicates the interrupt is disabled. 1h (W) = On a write, no effect. 1h (R) = On a read, indicates the interrupt is enabled. ® SWRU543 – January 2019 Cortex -M4 Peripherals Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 91: Pend_0 To Pend_6 Register
1h (W) = On a write, the corresponding interrupt is set to pending even if it is disabled. 1h (R) = On a read, indicates that the interrupt is pending. SWRU543 – January 2019 ® Cortex -M4 Peripherals Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 92: Unpend_0 To Unpend_6 Register
UNPEND4) register; PEND5 (for UNPEND5) register; PEND6 (for UNPEND6) register; so that interrupt [n] is no longer pending. 1h (R) = On a read, indicates that the interrupt is pending. ® SWRU543 – January 2019 Cortex -M4 Peripherals Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 93: Active_0 To Active_6 Register
Description 31-0 Interrupt Active 0h = The corresponding interrupt is not active. 1h = The corresponding interrupt is active, or active and pending. SWRU543 – January 2019 ® Cortex -M4 Peripherals Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 94: Pri_0 To Pri_49 Register
[4n], where n is the number of the Interrupt Priority register (n=0 for PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. RESERVED ® SWRU543 – January 2019 Cortex -M4 Peripherals Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 95: Cpuid Register
C24h = Cortex-M4 application processor in CC32xx. Revision Number 1h = The pn value in the rnpn product revision identifier; for example, the 1 in r0p1. SWRU543 – January 2019 ® Cortex -M4 Peripherals Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 96: Intctrl Register
1h (W) = On a write, changes the SysTick exception state to pending. 1h (R) = On a read, indicates a SysTick exception is pending. ® SWRU543 – January 2019 Cortex -M4 Peripherals Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 97 Interrupt Set Enable (ENn), Interrupt Clear Enable (DISn), Interrupt Set Pending (PENDn), Interrupt Clear Pending (UNPENDn), and Interrupt Priority (PRIn) registers. SWRU543 – January 2019 ® Cortex -M4 Peripherals Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 98: Vtable Register
Because there are 199 interrupts, the offset must be aligned on a 1024-byte boundary. RESERVED ® SWRU543 – January 2019 Cortex -M4 Peripherals Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 99: Apint Register
On a read, 0xFA05 is returned. ENDIANESS Data Endianess The CC32xx implementation uses only little-endian mode, so this is cleared to 0. 14-11 RESERVED SWRU543 – January 2019 ® Cortex -M4 Peripherals Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 100 This bit is reserved for debug use and reads as 0. This bit must be written as a 0, otherwise behavior is unpredictable. ® SWRU543 – January 2019 Cortex -M4 Peripherals Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 101: Sysctrl Register
Thread mode. 1h = When returning from Handler mode to Thread mode, enter sleep or deep sleep on return from an ISR. RESERVED SWRU543 – January 2019 ® Cortex -M4 Peripherals Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 102: Cfgctrl Register
0h = Do not trap on divide by 0. A divide by zero returns a quotient of 0. 1h = Trap on divide by 0. ® SWRU543 – January 2019 Cortex -M4 Peripherals Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 103 0h = The processor can enter Thread mode only when no exception is active. 1h = The processor can enter Thread mode from any level under the control of an EXC_RETURN value. SWRU543 – January 2019 ® Cortex -M4 Peripherals Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 104: Syspri1 Register
This field configures the priority level of the memory management fault. Configurable priority values are in the range 0-7, with lower values having higher priority. RESERVED ® SWRU543 – January 2019 Cortex -M4 Peripherals Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 105: Syspri2 Register
This field configures the priority level of SVCall. Configurable priority values are in the range 0-7, with lower values having higher priority. 28-0 RESERVED SWRU543 – January 2019 ® Cortex -M4 Peripherals Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 106: Syspri3 Register
This field configures the priority level of Debug. Configurable priority values are in the range 0-7, with lower values having higher priority. RESERVED ® SWRU543 – January 2019 Cortex -M4 Peripherals Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 107: Syshndctrl Register
1h = Enables the bus fault exception. Memory Management Fault Enable 0h = Disables the memory management fault exception. 1h = Enables the memory management fault exception. SWRU543 – January 2019 ® Cortex -M4 Peripherals Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 108: Syshndctrl Register Field Descriptions
Caution above before setting this bit. 0h = Bus fault is not active. 1h = Bus fault is active. ® SWRU543 – January 2019 Cortex -M4 Peripherals Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 109 Caution above before setting this bit. 0h = Memory management fault is not active. 1h = Memory management fault is active. SWRU543 – January 2019 ® Cortex -M4 Peripherals Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 110: Faultstat Register
R-0h R/W1C-0h R/W1C-0h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset ® SWRU543 – January 2019 Cortex -M4 Peripherals Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 111: Faultstat Register Field Descriptions
0h = A usage fault has not been caused by an undefined instruction. 1h = The processor has attempted to execute an undefined instruction. SWRU543 – January 2019 ® Cortex -M4 Peripherals Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 112 FAULTADDR register. This bit is cleared by writing a 1 to it. 0h = An instruction bus error has not occurred. 1h = An instruction bus error has occurred. ® SWRU543 – January 2019 Cortex -M4 Peripherals Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 113 0h = An instruction access violation has not occurred. 1h = The processor attempted an instruction fetch from a location that does not permit execution. SWRU543 – January 2019 ® Cortex -M4 Peripherals Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 114: Hfaultstat Register
0h = No bus fault has occurred on a vector table read. 1h = A bus fault occurred on a vector table read. RESERVED ® SWRU543 – January 2019 Cortex -M4 Peripherals Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 115: Faultddr Register
Fault Address When the FAULTADDRV bit of BFAULTSTAT is set, this field holds the address of the location that generated the bus fault. SWRU543 – January 2019 ® Cortex -M4 Peripherals Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 116: Swtrig Register
Interrupt ID This field holds the interrupt ID of the required SGI. For example, a value of 0x3 generates an interrupt on IRQ3. ® SWRU543 – January 2019 Cortex -M4 Peripherals Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 117 Chapter 4 SWRU543 – January 2019 Direct Memory Access (DMA) ........................... Topic Page ......................Overview ..................Functional Description ..................Register Description SWRU543 – January 2019 Direct Memory Access (DMA) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 118 The µDMA controller also supports the use of ping-pong buffering to accommodate constant streaming of data to or from a peripheral. Direct Memory Access (DMA) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 119: Dma Channel Assignment
GPIO A0 Software GPIO A1 Software Software GSPI (RX) SDHOST RX I2C A0 RX Software GSPI (TX) SDHOST TX I2C A0 TX Software SWRU543 – January 2019 Direct Memory Access (DMA) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 120 Any unused memory in the control table may be used by the application. This includes the control structures for any channels that are unused by the application, as well as the unused control word for each channel. Direct Memory Access (DMA) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 121: Channel Control Memory
Channel Enable Set (ENASET) register. A channel can be disabled by setting the channel bit in the DMA Channel Enable Clear (ENACLR) register. At the end of a complete µDMA transfer, the controller automatically disables the channel. SWRU543 – January 2019 Direct Memory Access (DMA) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 122 Data flow can continue indefinitely this way, using the primary and alternate control structures to switch between buffers as the data flows to or from the peripheral. Direct Memory Access (DMA) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 123: Ping-Pong Mode
Primary Structure CONTROL Unused SOURCE Process data in BUFFER B transfers using BUFFER B DEST BUFFER B Reload alternate structure Alternate Structure CONTROL Unused SWRU543 – January 2019 Direct Memory Access (DMA) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 124: Memory Scatter-Gather Mode
(3) Application sets up the channel primary control structure to copy each task configuration, one at a time, to the alternate control structure, where it is executed by the µDMA controller Direct Memory Access (DMA) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 125: Peripheral Scatter-Gather Mode
(8, 16, or 32 bits). Table 4-4 shows the configuration to read from a peripheral that supplies 8-bit data. SWRU543 – January 2019 Direct Memory Access (DMA) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 126 Any channel may be used for software requests, as long as the corresponding peripheral is not using the µDMA controller for data transfer. Direct Memory Access (DMA) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 127: Μdma Register Map
DMA Channel Primary Alternate Set 0x034 DMA_ALTCLR DMA Channel Primary Alternate Clear 0x038 DMA_PRIOSET 0x0000.0000 DMA Channel Priority Set 0x03C DMA_PRIOCLR DMA Channel Priority Clear SWRU543 – January 2019 Direct Memory Access (DMA) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 128: Dm Registers
DMA Channel Source Address End Pointer Section 4.3.3.1 DMA_DSTENDP DMA Channel Destination Address End Pointer Section 4.3.3.2 DMA_CHCTL DMA Channel Control Word Section 4.3.3.3 Direct Memory Access (DMA) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 129: Dma_Srcendp Register
If the destination address is not incrementing (the DSTINC field in the DMACHCTL register is 0x3), then this field points at the source location itself (such as a peripheral data register). SWRU543 – January 2019 Direct Memory Access (DMA) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 130: Dma_Chctl Register
2h = Word Increment by 32-bit location 3h = No increment Address remains set to the value of the Destination Address End Pointer (DMADSTENDP) for the channel 23-18 RESERVED Direct Memory Access (DMA) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 131 3h = Ping-pong 4h = Memory Scatter-Gather 5h = Alternate memory scatter gather 6h = Peripheral scatter gather 7h = Alternate peripheral scatter gather SWRU543 – January 2019 Direct Memory Access (DMA) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 132: Dma_(Offset_From_Dma_Base_Address) Registers
DMA Channel Map Select 2 Section 4.3.4.21 51Ch DMA_CHMAP3 DMA Channel Map Select 3 Section 4.3.4.22 FB0h DMA_PV DMA Peripheral Version Section 4.3.4.23 Direct Memory Access (DMA) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 133: Dma_Stat Register
8h = Stalled 9h = Done RESERVED MASTEN Master enable status. 0h = DMA controller is disabled 1h = DMA controller is enabled SWRU543 – January 2019 Direct Memory Access (DMA) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 134: Dma_Cfg Register
Table 4-12. DMA_CFG Register Field Descriptions Field Type Reset Description 31-1 RESERVED MASTEN Controller Master enable 0h = Disables DMA controller 1h = Enables DMA controller Direct Memory Access (DMA) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 135: Dma_Ctlbase Register
Channel Control Base Address. This field contains the pointer to the base address of the channel control table. The base address must be 1024-byte aligned. RESERVED SWRU543 – January 2019 Direct Memory Access (DMA) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 136: Dma_Altbase Register
Table 4-14. DMA_ALTBASE Register Field Descriptions Field Type Reset Description 31-0 ADDR Alternate Channel Address. This field provides the base address of the alternate channel control structures Direct Memory Access (DMA) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 137: Dma_Waitstat Register
Bit 0 corresponds to channel 0. 0h = The corresponding channel is not waiting on a request. 1h = The corresponding channel is waiting on a request. SWRU543 – January 2019 Direct Memory Access (DMA) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 138: Dma_Swreq Register
These bits are automatically cleared when the software request has been completed. 0h = No request generated 1h = Generate a software request for the corresponding channel. Direct Memory Access (DMA) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 139: Dma_Useburstset Register
CLR[n] bit in the DMAUSEBURSTCLR register. 0h = DMA channel [n] responds to single or burst requests. 1h = DMA channel [n] responds only to burst requests SWRU543 – January 2019 Direct Memory Access (DMA) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 140: Dma_Useburstclr Register
1h = Setting a bit clears the corresponding SET[n] bit in the DMAUSEBURSTSET register meaning that DMA channel [n] responds to single and burst requests Direct Memory Access (DMA) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 141: Dma_Reqmaskset Register
1h = The peripheral associated with channel [n] is not able to request DMA transfers. Channel [n] may be used for software- initiated transfers. SWRU543 – January 2019 Direct Memory Access (DMA) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 142: Dma_Reqmaskclr Register
1h = Setting a bit clears the corresponding SET[n] bit in the DMAREQMASKSET register meaning that the peripheral associated with channel [n] is enabled to request DMA transfers. Direct Memory Access (DMA) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 143: Dma_Enaset Register
DMAENACLR register or when the end of a DMA transfer occurs. 0h = DMA Channel [n] is disabled. 1h = DMA Channel [n] is enabled. SWRU543 – January 2019 Direct Memory Access (DMA) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 144: Dma_Enaclr Register
1h = Setting a bit clears the corresponding SET[n] bit in the DMAENASET register meaning that channel [n] is disabled for DMA transfers Direct Memory Access (DMA) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 145: Dma_Altset Register
Channel [n] Alternate Set 0h = DMA channel [n] is using the primary control structure 1h = DMA channel [n] is using the alternate control structure SWRU543 – January 2019 Direct Memory Access (DMA) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 146: Dma_Altclr Register
1h = Setting a bit clears the corresponding SET[n] bit in the DMAALTSET register meaning that channel [n] is using the primary control structure Direct Memory Access (DMA) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 147: Dma_Prioset Register
Channel [n] Priority Set 0h = DMA channel [n] is using the default priority level 1h = DMA channel [n] is using the high priority level SWRU543 – January 2019 Direct Memory Access (DMA) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 148: Dma_Prioclr Register
1h = Setting a bit clears the corresponding SET[n] bit in the DMAPRIOSET register meaning that channel [n] is using the default priority level Direct Memory Access (DMA) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 149: Dma_Errclr Register
Description 31-1 RESERVED ERRCLR R/W1C DMA Bus Error Status 0h = No bus error is pending. 1h = A bus error is pending. SWRU543 – January 2019 Direct Memory Access (DMA) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 150: Dma_Chasgn Register
Type Reset Description 31-0 CHASGN_n Channel [n] Assignment Select 0h = Use the primary channel assignment. 1h = Use the secondary channel assignment. Direct Memory Access (DMA) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 151: Dma_Chmap0 Register
DMA channel 3 source select 11-8 CH2SEL_n DMA channel 2 source select CH1SEL_n DMA channel 1 source select CH0SEL_n DMA channel 0 source select SWRU543 – January 2019 Direct Memory Access (DMA) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 152: Dma_Chmap1 Register
DMA channel 11 source select 11-8 CH10SEL_n DMA channel 10 source select CH9SEL_n DMA channel 9 source select CH8SEL_n DMA channel 8 source select Direct Memory Access (DMA) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 153: Dma_Chmap2 Register
DMA channel 19 source select 11-8 CH18SEL_n DMA channel 18 source select CH17SEL_n DMA channel 17 source select CH16SEL_n DMA channel 16 source select SWRU543 – January 2019 Direct Memory Access (DMA) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 154: Dma_Chmap3 Register
DMA channel 27 source select 11-8 CH26SEL_n DMA channel 26 source select CH25SEL_n DMA channel 25 source select CH24SEL_n DMA channel 24 source select Direct Memory Access (DMA) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 155: Dma_Pv Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 4-33. DMA_PV Register Field Descriptions Field Type Reset Description 31-16 RESERVED 15-8 MAJVER Major Version MINVER Minor Version SWRU543 – January 2019 Direct Memory Access (DMA) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 156 SWRU543 – January 2019 General-Purpose Input/Outputs (GPIOs) ........................... Topic Page ......................Overview ..................Functional Description ....................Interrupt Control ................Initialization and Configuration ....................GPIO Registers General-Purpose Input/Outputs (GPIOs) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 157: Digital I/O Pads
GPIOs are a subset of these 32 GPIO signals. For details on the usable GPIOs, refer to Table 16-6. Figure 5-1. Digital I/O Pads SWRU543 – January 2019 General-Purpose Input/Outputs (GPIOs) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 158: Gpiodata Write Example
GPIODATA bits 5, 4, and 0 with a single operation by using GPIODATA address alias 0x0C4 (offset address with regard to the base of the respective GPIO instance S0 to S4). Figure 5-3. GPIODATA Read Example General-Purpose Input/Outputs (GPIOs) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 159 Use the DATA register to drive the required value on the GPIO pin (when DIR = 1) or to read a value on the GPIO pin (when DIR = 0). Table 5-1 provides GPIO pad configuration examples, and Table 5-2 provides GPIO interrupt configuration examples. SWRU543 – January 2019 General-Purpose Input/Outputs (GPIOs) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 160: Gpio Pad Configuration Examples
1 = both edges 0 = low level, or falling edge GPIOIEV 1 = high level, or rising edge 0 = masked GPIOIM 1 = not masked General-Purpose Input/Outputs (GPIOs) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 161: Gpio Registers
GPIO Interrupt Clear Section 5.5.9 GPIO_TRIG_EN GPIO Trigger Enable Section 5.5.10 This register is outside of the GPIO module. The physical address is 0x400F 70C8. SWRU543 – January 2019 General-Purpose Input/Outputs (GPIOs) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 162: Gpiodata Register
Writes to this register only affect bits that are not masked by ADDR[9:2] and are configured as outputs. General-Purpose Input/Outputs (GPIOs) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 163: Gpiodir Register
Table 5-5. GPIODIR Register Field Descriptions Field Type Reset Description 31-8 RESERVED GPIO Data Direction 0h = Corresponding pin is an input. 1h = Corresponding pins is an output. SWRU543 – January 2019 General-Purpose Input/Outputs (GPIOs) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 164: Gpiois Register
GPIO Interrupt Sense 0h = The edge on the corresponding pin is detected (edge- sensitive). 1h = The level on the corresponding pin is detected (level-sensitive). General-Purpose Input/Outputs (GPIOs) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 165: Gpioibe Register
0h = Interrupt generation is controlled by the GPIO Interrupt Event (GPIOIEV) register. 1h = Both edges on the corresponding pin trigger an interrupt. SWRU543 – January 2019 General-Purpose Input/Outputs (GPIOs) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 166: Gpioiev Register
0h = A falling edge or a Low level on the corresponding pin triggers an interrupt. 1h = A rising edge or a High level on the corresponding pin triggers an interrupt. General-Purpose Input/Outputs (GPIOs) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 167: Gpioim Register
0h = The interrupt from the corresponding pin is masked. 1h = The interrupt from the corresponding pin is sent to the interrupt controller. SWRU543 – January 2019 General-Purpose Input/Outputs (GPIOs) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 168: Gpioris Register
0h = An interrupt condition has not occurred on the corresponding pin. 1h = An interrupt condition has occurred on the corresponding pin. General-Purpose Input/Outputs (GPIOs) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 169: Gpiomis Register
0h = An interrupt condition on the corresponding pin is masked or has not occurred. 1h = An interrupt condition on the corresponding pin has triggered an interrupt to the interrupt controller. SWRU543 – January 2019 General-Purpose Input/Outputs (GPIOs) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 170: Gpioicr Register
Table 5-12. GPIOICR Register Field Descriptions Field Type Reset Description 31-8 RESERVED GPIO Interrupt Clear 0h = The corresponding interrupt is unaffected. 1h = The corresponding interrupt is cleared. General-Purpose Input/Outputs (GPIOs) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 171: Gpio_Trig_En Register
GPIOA1 GPIO_14 GPIOA1 GPIO_15 GPIOA2 GPIO_16 GPIOA2 GPIO_17 GPIOA2 GPIO_18 (reserved) GPIOA2 GPIO_19 (reserved) GPIOA2 GPIO_20 (reserved) GPIOA2 GPIO_21 (reserved) GPIOA2 GPIO_22 GPIOA2 GPIO_23 SWRU543 – January 2019 General-Purpose Input/Outputs (GPIOs) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 172 GPIO_26 (Restricted use; Antenna Selection 1 only) GPIOA3 GPIO_27 (Restricted use; Antenna Selection 2 only) GPIOA3 GPIO_28 GPIOA3 GPIO_29 GPIOA3 GPIO_30 (PM/Dig Mux) GPIOA3 GPIO_31 (PM/Dig Mux) GPIOA4 GPIO_32 General-Purpose Input/Outputs (GPIOs) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 173 Chapter 6 SWRU543 – January 2019 Universal Asynchronous Receivers/Transmitters (UARTs) ........................... Topic Page ......................Overview ..................Functional Description ....................UART Registers SWRU543 – January 2019 Universal Asynchronous Receivers/Transmitters (UARTs) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 174 – Transmit single request asserted when there is space in the FIFO; burst request asserted at programmed FIFO level • System clock generates the baud clock. 6.1.1 Block Diagram Figure 6-1 shows the UART module block diagram. Universal Asynchronous Receivers/Transmitters (UARTs) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 175: Uart Module Block Diagram
Overrun, parity, frame error checking, and line-break detection are also performed, and their status accompanies the data written to the RX FIFO. SWRU543 – January 2019 Universal Asynchronous Receivers/Transmitters (UARTs) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 176: Uart Character Frame
Baud16 or the fourth cycle of Baud8 depending on the setting of the HSE bit (bit 5) in UARTCTL. Universal Asynchronous Receivers/Transmitters (UARTs) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 177: Flow Control Mode
OE bit. If the FIFOs are disabled, the empty and full flags are set according to the status of the 1-byte-deep holding registers. SWRU543 – January 2019 Universal Asynchronous Receivers/Transmitters (UARTs) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 178 UARTCTL register. In loopback mode, data transmitted on the UnTx output is received on the UnRx input. The LBE bit must be set before the UART is enabled. Universal Asynchronous Receivers/Transmitters (UARTs) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 179 DIVINT field of the UARTIBRD register should be set to 43 decimal or 0x2B. The value to be loaded into the UARTFBRD register is calculated by Equation UARTFBRD[DIVFRAC] = integer(0.410590 × 64 + 0.5) = 26 SWRU543 – January 2019 Universal Asynchronous Receivers/Transmitters (UARTs) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 180 5. Optionally, configure the µDMA channel and enable the DMA options in the UARTDMACTL register. 6. Enable the UART by setting the UARTEN bit in the UARTCTL register. Universal Asynchronous Receivers/Transmitters (UARTs) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 181: Uart Registers
UART Raw Interrupt Status Section 6.3.10 UARTMIS UART Masked Interrupt Status Section 6.3.11 UARTICR UART Interrupt Clear Section 6.3.12 UARTDMACTL UART DMA Control Section 6.3.13 SWRU543 – January 2019 Universal Asynchronous Receivers/Transmitters (UARTs) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 182: Uartdr Register
Data that is to be transmitted through the UART is written to this field. When read, this field contains the data that was received by the UART. Universal Asynchronous Receivers/Transmitters (UARTs) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 183: Uartrsr_Uartecr Register
FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received. SWRU543 – January 2019 Universal Asynchronous Receivers/Transmitters (UARTs) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 184: Uartrsr_Uartecr Register Field Descriptions
1h (R) = The received character does not have a valid stop bit (a valid stop bit is 1). In FIFO mode, this error is associated with the character at the top of the FIFO. Universal Asynchronous Receivers/Transmitters (UARTs) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 185: Uartfr Register
0h = The receiver is not empty. 1h = If the FIFO is disabled (FEN is 0), the receive holding register is empty. SWRU543 – January 2019 Universal Asynchronous Receivers/Transmitters (UARTs) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 186 This bit is implemented only on UART1 and is reserved for UART0 0h = The U1CTS signal is not asserted. 1h = The U1CTS signal is asserted. Universal Asynchronous Receivers/Transmitters (UARTs) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 187: Uartibrd Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 6-6. UARTIBRD Register Field Descriptions Field Type Reset Description 31-16 RESERVED 15-0 DIVINT Integer Baud-Rate Divisor SWRU543 – January 2019 Universal Asynchronous Receivers/Transmitters (UARTs) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 188: Uartfbrd Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 6-7. UARTFBRD Register Field Descriptions Field Type Reset Description 31-6 RESERVED DIVFRAC Fractional Baud-Rate Divisor Universal Asynchronous Receivers/Transmitters (UARTs) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 189: Uartlcrh Register
1h = Two stop bits are transmitted at the end of a frame. The receive logic does not check for two stop bits being received. SWRU543 – January 2019 Universal Asynchronous Receivers/Transmitters (UARTs) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 190 For the proper execution of the break command, software must set this bit for at least two frames (character periods). Universal Asynchronous Receivers/Transmitters (UARTs) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 191: Uartctl Register
1h = RTS hardware flow control is enabled. Data is only requested (by asserting U1RTS) when the receive FIFO has available entries. 13-12 RESERVED SWRU543 – January 2019 Universal Asynchronous Receivers/Transmitters (UARTs) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 192 If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. 0h = The UART is disabled. 1h = The UART is enabled. Universal Asynchronous Receivers/Transmitters (UARTs) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 193: Uartifls Register
FIFO is completely empty and all data including stop bits have left the transmit serializer. In this case, the setting of TXIFLSEL is ignored. SWRU543 – January 2019 Universal Asynchronous Receivers/Transmitters (UARTs) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 194: Uartim Register
0h = The BERIS interrupt is suppressed and not sent to the interrupt controller. 1h = An interrupt is sent to the interrupt controller when the BERIS bit in the UARTRIS register is set. Universal Asynchronous Receivers/Transmitters (UARTs) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 195 1h = An interrupt is sent to the interrupt controller when the CTSRIS bit in the UARTRIS register is set. RIIM Reserved SWRU543 – January 2019 Universal Asynchronous Receivers/Transmitters (UARTs) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 196: Uartris Register
This bit is cleared by writing a 1 to the PEIC bit in the UARTICR register. 0h = No interrupt 1h = A parity error has occurred. Universal Asynchronous Receivers/Transmitters (UARTs) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 197 This bit is cleared by writing a 1 to the CTSIC bit in the UARTICR register. 0h = No interrupt 1h = Clear to Send used for software flow control. RIRIS Reserved SWRU543 – January 2019 Universal Asynchronous Receivers/Transmitters (UARTs) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 198: Uartmis Register
0h = An interrupt has not occurred or is masked. 1h = An unmasked interrupt was signaled due to a parity error. Universal Asynchronous Receivers/Transmitters (UARTs) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 199 0h = An interrupt has not occurred or is masked. 1h = An unmasked interrupt was signaled due to Clear to Send. RIMIS Reserved SWRU543 – January 2019 Universal Asynchronous Receivers/Transmitters (UARTs) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 200: Uarticr Register
Receive Interrupt Clear Writing a 1 to this bit clears the RXRIS bit in the UARTRIS register and the RXMIS bit in the UARTMIS register. Universal Asynchronous Receivers/Transmitters (UARTs) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 201 Writing a 1 to this bit clears the CTSRIS bit in the UARTRIS register and the CTSMIS bit in the UARTMIS register. RIMIC Reserved SWRU543 – January 2019 Universal Asynchronous Receivers/Transmitters (UARTs) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 202: Uartdmactl Register
1h = DMA for the receive FIFO is enabled. RXDMAE Receive DMA Enable 0h = DMA for the receive FIFO is disabled. 1h = DMA for the receive FIFO is enabled. Universal Asynchronous Receivers/Transmitters (UARTs) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 203 Chapter 7 SWRU543 – January 2019 Inter-Integrated Circuit (I C) Interface ........................... Topic Page ......................Overview ..................Functional Description ....................I2C Registers SWRU543 – January 2019 Inter-Integrated Circuit (I C) Interface Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 204 – Ability to execute single data transfers or burst data transfers using the RX and TX FIFOs in the module? 7.1.1 Block Diagram Figure 7-1 shows the I2C block diagram. SWRU543 – January 2019 Inter-Integrated Circuit (I C) Interface Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 205: I2C Block Diagram
The CONFMODE bits in the GPIO_PAD_CONFIG register should be set to choose the I2C function. Set the I2CSDA and I2CSCL pins to open-drain using the IODEN bits of the GPIO_PAD_CONFIG register. SWRU543 – January 2019 Inter-Integrated Circuit (I C) Interface Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 206: I2C Bus Configuration
SDA line while SCL is high is defined as a STOP condition. The bus is considered busy after a START condition and free after a STOP condition (see Figure 7-3). SWRU543 – January 2019 Inter-Integrated Circuit (I C) Interface Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 207: Start And Stop Conditions
The data on the SDA line must be stable during the high period of the clock, and the data line can only change when SCL is low (see Figure 7-6). SWRU543 – January 2019 Inter-Integrated Circuit (I C) Interface Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 208: Data Validity During Bit Transfer On The I2C Bus
4. The master does not generate a STOP condition, but instead writes another slave address to the I2CMSA register, then writes 0x3 to initiate the repeated START. SWRU543 – January 2019 Inter-Integrated Circuit (I C) Interface Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 209 The OAR2SEL bit in the I2CSCSR register indicates if the ACKed address is the alternate address or not. When this bit is clear, it indicates either legacy operation or no address match. SWRU543 – January 2019 Inter-Integrated Circuit (I C) Interface Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 210: Timer Periods
Table 7-2. Timer Periods System Clock Timer Period Standard Mode Timer Period Fast Mode 80 MHz 0x27 100 kbps 0x09 400 kbps SWRU543 – January 2019 Inter-Integrated Circuit (I C) Interface Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 211 The TX and RX FIFOs can be assigned to the slave. • The TX FIFO can be assigned to the master, while the RX FIFO is assigned to the slave, and vice SWRU543 – January 2019 Inter-Integrated Circuit (I C) Interface Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 212 TX FIFO fill level is less than the trigger set). If the I2CMBLEN register value is less than 4 and the TX FIFO is not full but more than the trigger level, only dma_sreq asserts. Single requests are SWRU543 – January 2019 Inter-Integrated Circuit (I C) Interface Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 213 Figure 7-9, Figure 7-10, Figure 7-11, and Figure 7-12 show the flow charts of command sequences available for the I C master. SWRU543 – January 2019 Inter-Integrated Circuit (I C) Interface Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 214: Master Single Transmit
Write data to system I2CMDR Read I2CMCS BUSBSY bit=0? Write ---0-111 to I2CMCS Read I2CMCS BUSY bit=0? Error Service ERROR bit=0? Idle SWRU543 – January 2019 Inter-Integrated Circuit (I C) Interface Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 215: Master Single Receive
I2CMSA Read I2CMCS BUSBSY bit=0? Write ---00111 to I2CMCS Read I2CMCS BUSY bit=0? Error Service ERROR bit=0? Read data from I2CMDR Idle SWRU543 – January 2019 Inter-Integrated Circuit (I C) Interface Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 216: Master Transmit Of Multiple Data Bytes
Write ---0-001 to I2CMCS Index=n? to I2CMCS Error Service Write ---0-101 to I2CMCS Idle Read I2CMCS BUSY bit=0? Error Service ERROR bit=0? Idle SWRU543 – January 2019 Inter-Integrated Circuit (I C) Interface Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 217: Master Receive Of Multiple Data Bytes
I2CMCS Error Service Write ---00101 to I2CMCS Idle Read I2CMCS BUSY bit=0? ERROR bit=0? Read data from Error Service I2CMDR Idle SWRU543 – January 2019 Inter-Integrated Circuit (I C) Interface Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 218: Master Receive With Repeated Start After Master Transmit
Address to I2CMSA Write ---01011 to I2CMCS Repeated START condition is generated with changing data Master operates in direction Master Receive mode Idle SWRU543 – January 2019 Inter-Integrated Circuit (I C) Interface Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 219: Master Transmit With Repeated Start After Master Receive
Address to I2CMSA Write ---0-011 to I2CMCS Repeated START condition is generated with changing data Master operates in direction Master Transmit mode Idle SWRU543 – January 2019 Inter-Integrated Circuit (I C) Interface Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 220: Slave Command Sequence
Write ------ 1 to I2CSCSR Read I2CSCSR TREQ bit=1? RREQ bit=1? FBR is also valid Write data to Read data from I2CSDR I2CSDR SWRU543 – January 2019 Inter-Integrated Circuit (I C) Interface Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 221 9. Wait until the transmission completes by polling the BUSBSY bit of the I2CMCS register until the bit has been cleared. 10. Check the ERROR bit in the I2CMCS register to confirm the transmit was acknowledged. SWRU543 – January 2019 Inter-Integrated Circuit (I C) Interface Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 222: I2C Registers
Section 7.3.24 F08h I2CFIFOSTATUS I2C FIFO Status Section 7.3.25 FC0h I2CPP I2C Peripheral Properties Section 7.3.26 FC4h I2CPC I2C Peripheral Configuration Section 7.3.27 SWRU543 – January 2019 Inter-Integrated Circuit (I C) Interface Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 223: I2Cmsa Register
The R/S bit specifies if the next master operation is a Receive (High) or Transmit (Low). 0h = Transmit 1h = Receive SWRU543 – January 2019 Inter-Integrated Circuit (I C) Interface Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 224: I2Cmcs Register
0h (R) = The I2C controller is not idle. 1h (W) = The bus transaction is a quick command. 1h (R) = The I2C controller is idle. SWRU543 – January 2019 Inter-Integrated Circuit (I C) Interface Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 225 1h (W) = The master is able to transmit or receive data. Note that this bit cannot be set in burst mode. 1h (R) = The controller is busy. SWRU543 – January 2019 Inter-Integrated Circuit (I C) Interface Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 226: Write Field Decoding For I2Cmcs[6:0]
ACK; followed by High-Speed Burst transmit Operation. Illegal Illegal An X in a table cell indicates the bit can be 0 or 1. SWRU543 – January 2019 Inter-Integrated Circuit (I C) Interface Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 227 (master goes to Idle state). Repeated START condition followed by N FIFO- serviced RECEIVE operations (master goes to Master Receive state). Illegal Illegal SWRU543 – January 2019 Inter-Integrated Circuit (I C) Interface Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 228 In Master Receive mode, a STOP condition should be generated only after a Data Negative Acknowledge executed by the master, or an Address Negative Acknowledge executed by the slave. SWRU543 – January 2019 Inter-Integrated Circuit (I C) Interface Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 229: I2Cmdr Register
Table 7-7. I2CMDR Register Field Descriptions Field Type Reset Description 31-8 RESERVED DATA This byte contains the data transferred during a transaction. SWRU543 – January 2019 Inter-Integrated Circuit (I C) Interface Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 230: I2Cmtpr Register
SCL_LP is the SCL Low period (fixed at 6) SCL_HP is the SCL High period (fixed at 4) CLK_PRD is the system clock period in ns. SWRU543 – January 2019 Inter-Integrated Circuit (I C) Interface Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 231: I2Cmimr Register
1h = The TX FIFO Request interrupt is sent to the interrupt controller when the TXRIS bit in the I2CMRIS register is set. SWRU543 – January 2019 Inter-Integrated Circuit (I C) Interface Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 232 1h = The master interrupt is sent to the interrupt controller when the RIS bit in the I2CMRIS register is set. SWRU543 – January 2019 Inter-Integrated Circuit (I C) Interface Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 233: I2Cmris Register
1h = The trigger level for the TX FIFO has been reached and more data is needed to complete the burst. Thus, a TX FIFO request interrupt is pending. SWRU543 – January 2019 Inter-Integrated Circuit (I C) Interface Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 234 This bit is cleared by writing a 1 to the IC bit in the I2CMICR register. 0h = No interrupt. 1h = A master interrupt is pending. SWRU543 – January 2019 Inter-Integrated Circuit (I C) Interface Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 235: I2Cmmis Register
This bit is cleared by writing a 1 to the ARBLOSTIC bit in the I2CMICR register. 0h = No interrupt. 1h = An unmasked Arbitration Lost interrupt was signaled and is pending. SWRU543 – January 2019 Inter-Integrated Circuit (I C) Interface Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 236 This bit is cleared by writing a 1 to the CLKIC bit in the I2CMICR register. 0h = No interrupt. 1h = An unmasked clock timeout interrupt was signaled and is pending. SWRU543 – January 2019 Inter-Integrated Circuit (I C) Interface Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 237: I2Cmicr Register
Writing a 1 to this bit clears the STARTRIS bit in the I2CMRIS register and the STARTMIS bit in the I2CMMIS register. A read of this register returns no meaningful data. SWRU543 – January 2019 Inter-Integrated Circuit (I C) Interface Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 238 Writing a 1 to this bit clears the RIS bit in the I2CMRIS register and the MIS bit in the I2CMMIS register. A read of this register returns no meaningful data. SWRU543 – January 2019 Inter-Integrated Circuit (I C) Interface Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 239: I2Cmcr Register
1h = Master mode is enabled. RESERVED LPBK I2C Loopback 0h = Normal operation. 1h = The controller in a test mode loopback configuration. SWRU543 – January 2019 Inter-Integrated Circuit (I C) Interface Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 240: I2Cmclkocnt Register
This field contains the upper 8 bits of a 12-bit counter for the clock low timeout count. Note: The value of CNTL must be greater than 0x1. SWRU543 – January 2019 Inter-Integrated Circuit (I C) Interface Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 241: I2Cmbmon Register
1h = The I2CSDA signal is high. I2C SCL Status 0h = The I2CSCL signal is low. 1h = The I2CSCL signal is high. SWRU543 – January 2019 Inter-Integrated Circuit (I C) Interface Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 242: I2Cmblen Register
This field contains the programmed length of bytes of the burst transaction. If BURST is enabled, this register must be set to a non- zero value, otherwise an error will occur. SWRU543 – January 2019 Inter-Integrated Circuit (I C) Interface Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 243: I2Cmbcnt Register
Field Type Reset Description 31-8 RESERVED CNTL I2C Master Burst Count This field contains the current count-down value of the BURST transaction. SWRU543 – January 2019 Inter-Integrated Circuit (I C) Interface Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 244: I2Csoar Register
Table 7-18. I2CSOAR Register Field Descriptions Field Type Reset Description 31-7 RESERVED I2C Slave Own Address This field specifies bits A6 through A0 of the slave address. SWRU543 – January 2019 Inter-Integrated Circuit (I C) Interface Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 245: I2Cscsr Register
1h (R) = The first byte following the slave s own address has been received. Note: This bit is not used for slave transmit operations. SWRU543 – January 2019 Inter-Integrated Circuit (I C) Interface Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 246 1h (R) = The I2C controller has outstanding receive data from the I2C master and is using clock stretching to delay the master until the data has been read from the I2CSDR register. SWRU543 – January 2019 Inter-Integrated Circuit (I C) Interface Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 247: I2Csdr Register
Reset Description 31-8 RESERVED DATA Data for Transfer This field contains the data for transfer during a slave receive or transmit operation. SWRU543 – January 2019 Inter-Integrated Circuit (I C) Interface Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 248: I2Csimr Register
1h = The receive DMA complete interrupt is sent to the interrupt controller when the DMARXRIS bit in the I2CSRIS register is set. SWRU543 – January 2019 Inter-Integrated Circuit (I C) Interface Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 249 0h = The DATARIS interrupt is suppressed and not sent to the interrupt controller. 1h = Data interrupt sent to interrupt controller when DATARIS bit in the I2CSRIS register is set. SWRU543 – January 2019 Inter-Integrated Circuit (I C) Interface Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 250: I2Csris Register
This bit is cleared by writing a 1 to the DMATXIC bit in the I2CSICR register. 0h = No interrupt 1h = A transmit DMA complete interrupt is pending. SWRU543 – January 2019 Inter-Integrated Circuit (I C) Interface Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 251 This bit is cleared by writing a 1 to the DATAIC bit in the I2CSICR register. 0h = No interrupt. 1h = Slave Interrupt is pending. SWRU543 – January 2019 Inter-Integrated Circuit (I C) Interface Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 252: I2Csmis Register
0h = An interrupt has not occurred or is masked. 1h = An unmasked transmit DMA complete interrupt was signaled is pending. SWRU543 – January 2019 Inter-Integrated Circuit (I C) Interface Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 253 0h = An interrupt has not occurred or is masked. 1h = An unmasked slave data interrupt was signaled is pending. SWRU543 – January 2019 Inter-Integrated Circuit (I C) Interface Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 254: I2Csicr Register
Writing a 1 to this bit clears the DMARXRIS bit in the I2CSRIS register and the DMARXMIS bit in the I2CSMIS register. A read of this register returns no meaningful data. SWRU543 – January 2019 Inter-Integrated Circuit (I C) Interface Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 255 Writing a 1 to this bit clears the STARTRIS bit in the I2CSRIS register and the STARTMIS bit in the I2CSMIS register. A read of this register returns no meaningful data. SWRU543 – January 2019 Inter-Integrated Circuit (I C) Interface Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 256: I2Csoar2 Register
1h = Enables the use of the alternate address in the OAR2 field. OAR2 I2C Slave Own Address 2 This field specifies the alternate OAR2 address. SWRU543 – January 2019 Inter-Integrated Circuit (I C) Interface Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 257: I2Csackctl Register
0h = A response in not provided. 1h = An ACK or NACK is sent according to the value written to the ACKOVAL bit. SWRU543 – January 2019 Inter-Integrated Circuit (I C) Interface Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 258: I2Cfifodata Register
This field contains the current byte written to the TX FIFO. For back to back transmit operations, the application should not switch between writing to the I2CSDR register and the I2CFIFODATA. SWRU543 – January 2019 Inter-Integrated Circuit (I C) Interface Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 259: I2Cfifoctl Register
1h = TX FIFO is assigned to Slave TXFLUSH TX FIFO Flush Setting this bit flushes the TX FIFO. This bit self-clears when the flush has completed. SWRU543 – January 2019 Inter-Integrated Circuit (I C) Interface Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 260 5h = Trigger when TX FIFO 5 bytes 6h = Trigger when TX FIFO 6 bytes 7h = Trigger when TX FIFO 7 bytes SWRU543 – January 2019 Inter-Integrated Circuit (I C) Interface Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 261: I2Cfifostatus Register
1h = The TX FIFO is full. TXFE TX FIFO Empty 0h = The TX FIFO is not empty. 1h = The TX FIFO is empty. SWRU543 – January 2019 Inter-Integrated Circuit (I C) Interface Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 262: I2Cpp Register
Type Reset Description 31-1 RESERVED High-Speed Capable 0h = The interface is capable of standard or fast mode operation. 1h = Reserved SWRU543 – January 2019 Inter-Integrated Circuit (I C) Interface Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 263: I2Cpc Register
High-Speed Capable 0h = The interface is capable of standard or fast mode operation. 1h = Reserved. Must be set to 0 SWRU543 – January 2019 Inter-Integrated Circuit (I C) Interface Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 264 ........................... Topic Page ......................Overview ..................Functional Description ................Initialization and Configuration .................. Access to Data Registers ..................Module Initialization ....................SPI Registers SPI (Serial Peripheral Interface) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 265: Spi Block Diagram
Serial clock with programmable frequency, polarity, and phase • SPI enable – Generation programmable – Programmable polarity • Selection of SPI word lengths at 8, 16, and 32 bits SWRU543 – January 2019 SPI (Serial Peripheral Interface) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 266 After eight cycles of the serial clock SPICLK, the WordA has been transferred from the master to the slave. At the same time, the WordB has been transferred from the slave to the master. SPI (Serial Peripheral Interface) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 267: Spi Full-Duplex Transmission (Example)
The baud rate of the SPI serial clock is programmable when the SPI is a master. When the SPI is operating as a slave, the serial clock SPICLK is an input from the external master. SWRU543 – January 2019 SPI (Serial Peripheral Interface) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 268: Phase And Polarity Combinations
This process continues for a total number of pulses on the SPICLK line defined by the SPI word length programmed in the master device, with data being latched on odd-numbered edges and shifted on even- numbered edges. SPI (Serial Peripheral Interface) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 269: Full-Duplex Single Transfer Format With Pha
SPI transfer for the SPI mode1 and SPI mode3, when the SPI is master or slave, with the frequency of SPICLK equal to the frequency of CLKSPIREF. SWRU543 – January 2019 SPI (Serial Peripheral Interface) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 270: Full-Duplex Single Transfer Format With Pha
The TX_underflow event is activated when the channel is enabled and the transmitter register or FIFO is empty (not updated with new data) at the time of a shift register assignment. TX_underflow acts as a warning in master mode. SPI (Serial Peripheral Interface) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 271 In 3-pin mode: the MCSPI_MODULCTRL[1] PIN34 and MCSPI_MODULCTRL[0] SINGLE bits are set to 1, and the controller transmits the SPI word when the transmit register or FIFO is not empty. SWRU543 – January 2019 SPI (Serial Peripheral Interface) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 272: Contiguous Transfers With Spien Kept Active (Two Data Pins Interface Mode)
Clock Ratio CLKSPIO High Time CLKSPIO Low Time ratio _ref _ref high Even ≥ 2 T_ref × (F T_ref × (F ratio ratio SPI (Serial Peripheral Interface) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 273: Granularity Examples
Then the system can access a 32- byte-deep FIFO per direction. See Figure 8-7, Figure 8-8, Figure 8-9, and Figure 8-10. SWRU543 – January 2019 SPI (Serial Peripheral Interface) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 274: Transmit/Receive Mode With No Fifo Used
SPI Domain Configuration: MCSPI_CH(i)CONF[TRM] = 0 (Transmit/receive mode) MCSPI_CH(i)CONF[FFER] = 1 (FIFO enabled on receive path) MCSPI_CH(i)CONF[FFEW] = 0 (FIFO disabled on transmit path) SPI (Serial Peripheral Interface) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 275: Transmit/Receive Mode With Only Transmit Fifo Used
SPI Domain Configuration: MCSPI_CH(i)CONF[TRM] = 0 (Transmit/receive mode) MCSPI_CH(i)CONF[FFER] = 1 (FIFO enabled on receive path) MCSPI_CH(i)CONF[FFEW] = 0 (FIFO disabled on transmit path) SWRU543 – January 2019 SPI (Serial Peripheral Interface) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 276: Buffer Almost Full Level (Afl)
(in bytes) Empty <MCSPI_IRQSTATUS[TiE]>* * non-DMA mode only. In DMA mode, the DMA TX request is asserted to its active level under identical conditions. SPI (Serial Peripheral Interface) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 277 The SPI is in slave mode when the MS bit of the SPI_MODULCTRL register is set. In slave mode, the SPI should be connected to only one external master device. SWRU543 – January 2019 SPI (Serial Peripheral Interface) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 278 When FIFO is enabled, the data emitted while the underflow event is raised is not the last data written in the FIFO. The TX_underflow event indicates an error (data loss) in slave mode. SPI (Serial Peripheral Interface) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 279 In this last case, the definition of the AEL and AFL levels is based on 64 bytes, and is the responsibility of the local host. SWRU543 – January 2019 SPI (Serial Peripheral Interface) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 280 DMA requests if enabled. The DMA requests must be disabled to get TX and RX interrupts. There are two DMA request lines for the channel. SPI (Serial Peripheral Interface) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 281 Enable SPI channel for communication: SPIEnable(GSPI_BASE) c. Enable chip select: SPICSEnable(GSPI_BASE) d. Write new data into TX FIFO to transmit over the interface: SPIDataPut(GSPI_BASE,<UserData>); SWRU543 – January 2019 SPI (Serial Peripheral Interface) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 282 This section describes the supported data accesses (read or write) to and from the data receiver registers SPI_RX and data transmitter registers SPI_TX. SPI (Serial Peripheral Interface) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 283: Flow Chart - Module Initialization
For all these flows, the host process contains the main process and the interrupt routines. The interrupt routines are called on the interrupt signals, or by an internal call if the module is used in polling mode. SWRU543 – January 2019 SPI (Serial Peripheral Interface) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 284: Flow Chart - Common Transfer Sequence
= 0 • channel_enable = FALSE • last_transfer = FALSE • last_request = FALSE These variables are initialized before starting the channel. SPI (Serial Peripheral Interface) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 285: Flow Chart - Transmit And Receive (Master And Slave)
In transmit and receive mode, the FIFO can be enabled for write or read request only. The SPI module starts the transfer only when the first write request is released, by writing the SPI_TX register. See Figure 8-17. SWRU543 – January 2019 SPI (Serial Peripheral Interface) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 286: Flow Chart - Fifo Mode Common Sequence (Master)
If they are not submultiples of N, the last request sizes are: • last_write_request_size (< write_request_size) • last_read_request_size. (< read_request_size) Figure 8-17. Flow Chart – FIFO Mode Common Sequence (Master) SPI (Serial Peripheral Interface) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 287 In these sequences, some soft variables are used: • write_count = N • read_count = N • last_request = FALSE These variables are initialized before starting the channel. SWRU543 – January 2019 SPI (Serial Peripheral Interface) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 288: Flow Chart - Fifo Mode Transmit And Receive With Word Count (Master)
Flow of a transfer in transmit – receive mode, with word count. Figure 8-18. Flow Chart – FIFO Mode Transmit and Receive With Word Count (Master) SPI (Serial Peripheral Interface) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 289: Flow Chart - Fifo Mode Transmit And Receive Without Word Count (Master)
Flow of a transfer in transmit – receive mode, without word count. Figure 8-19. Flow Chart – FIFO Mode Transmit and Receive without Word Count (Master) SWRU543 – January 2019 SPI (Serial Peripheral Interface) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 290: Spi Registers
SPI_CHCTRL Channel Control Section 8.6.8 138h SPI_TX Channel Transmitter Section 8.6.9 13Ch SPI_RX Channel Receiver Section 8.6.10 17Ch SPI_XFERLEVEL Transfer Levels Section 8.6.11 SPI (Serial Peripheral Interface) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 291: Spi_Sysconfig Register
0h (W) = No action 0h (R) = Reset done, no pending action 1h (W) = Initiate software reset 1h (R) = Reset (software or other) ongoing SWRU543 – January 2019 SPI (Serial Peripheral Interface) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 292: Spi_Sysstatus Register
Field Type Reset Description 31-1 RESERVED RESETDONE Internal Reset Monitoring 0h (R) = Internal module reset is on-going 1h (R) = Reset completed SPI (Serial Peripheral Interface) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 293: Spi_Irqstatus Register
0h (W) = Event status bit unchanged 0h (R) = Event false 1h (W) = Event status bit is reset 1h (R) = Event is pending SWRU543 – January 2019 SPI (Serial Peripheral Interface) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 294: Spi_Irqstatus Register Field Descriptions
0h (W) = Event status bit unchanged 0h (R) = Event false 1h (W) = Event status bit is reset 1h (R) = Event is pending SPI (Serial Peripheral Interface) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 295: Spi_Irqenable Register
0h = Interrupt disabled 1h = Interrupt enabled TX_EMPTY_ENABLE Transmitter register empty or almost empty interrupt enable. 0h = Interrupt disabled 1h = Interrupt enabled SWRU543 – January 2019 SPI (Serial Peripheral Interface) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 296: Spi_Modulctrl Register
Channel enable (master mode only) 1h = Channel will be used in master mode. This bit must be set in Force SPIEN mode. SPI (Serial Peripheral Interface) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 297: Spi_Chconf Register
FIFO enabled for transmit: Only one channel can have this bit field set. 0h = The buffer is not used to transmit data. 1h = The buffer is used to transmit data. 26-21 RESERVED SWRU543 – January 2019 SPI (Serial Peripheral Interface) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 298: Spi_Chconf Register Field Descriptions
EPOL SPIEN polarity 0h = SPIEN is held high during the active state. 1h = SPIEN is held low during the active state. SPI (Serial Peripheral Interface) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 299: Spi
SPICLK phase 0h = Data are latched on odd numbered edges of SPICLK. 1h = Data are latched on even numbered edges of SPICLK. SWRU543 – January 2019 SPI (Serial Peripheral Interface) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 300: Spi_Chstat Register
0h (R) = Register is full 1h (R) = Register is empty Channel receiver register status 0h (R) = Register is empty 1h (R) = Register is full SPI (Serial Peripheral Interface) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 301: Spi_Chctrl Register
FFh = Clock ratio is CLKD + 1 + 4080 RESERVED Channel enable 0h = Channel is not active 1h = Channel is active SWRU543 – January 2019 SPI (Serial Peripheral Interface) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 302: Spi_Tx Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 8-15. SPI_TX Register Field Descriptions Field Type Reset Description 31-0 TDATA Channel data to transmit SPI (Serial Peripheral Interface) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 303: Spi_Rx Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 8-16. SPI_RX Register Field Descriptions Field Type Reset Description 31-0 RDATA Channel data received SWRU543 – January 2019 SPI (Serial Peripheral Interface) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 304: Spi_Xferlevel Register
SPI_XFERLEVEL[AEL] must be set with n-1. 0h = 1 byte 1h = 2 bytes Fh = 16 bytes SPI (Serial Peripheral Interface) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 305 Chapter 9 SWRU543 – January 2019 General-Purpose Timers ........................... Topic Page ......................Overview ....................Block Diagram ..................Functional Description ................Initialization and Configuration ....................Timer Registers SWRU543 – January 2019 General-Purpose Timers Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 306 Runs from system clock (80 MHz) Block Diagram Figure 9-1 shows a block diagram of the GPTM. Table 9-1 lists the available CCP pins and the PWM outputs/signals pins. General-Purpose Timers SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 307: Gptm Module Block Diagram
Two prescaler registers • Two match registers • Two prescaler match registers • Two shadow registers • Two load/initialization registers and their associated control functions SWRU543 – January 2019 General-Purpose Timers Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 308: General-Purpose Timer Capabilities
GPTM Timer A Prescale (GPTMTAPR) register • GPTM Timer B Prescale (GPTMTBPR) register • GPTM Timer A Prescale Snapshot (GPTMTAPS) register • GPTM Timer B Prescale Snapshot (GPTMTBPS) register General-Purpose Timers SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 309: Counter Values When The Timer Is Enabled In Periodic Or One-Shot Modes
The µDMA trigger is enabled by configuring and enabling the appropriate µDMA channel, as well as the type of trigger enable in the GPTM DMA Event (GPTMDMAEV) register. SWRU543 – January 2019 General-Purpose Timers Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 310: Counter Values When The Timer Is Enabled In Input Edge-Count Mode
Table 9-5. Counter Values When the Timer is Enabled in Input Edge-Count Mode Register Count-Down Mode Count-Up Mode GPTMTnPR in combination with GPTMTnR GPTMTnILR GPTMTnPR in combination with GPTMTnV GPTMTnILR General-Purpose Timers SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 311: Input Edge-Count Mode Example, Counting Down
Based on this criteria, the maximum input frequency for edge detection is 1/4 of the system frequency. SWRU543 – January 2019 General-Purpose Timers Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 312: Counter Values When The Timer Is Enabled In Input Edge-Time Mode
GPTMTnPS registers, and is held there until another rising-edge is detected (at which point the new count value is loaded into the GPTMTnR and GPTMTnPS registers). Figure 9-3. 16-Bit Input Edge-Time Mode Example General-Purpose Timers SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 313: Counter Values When The Timer Is Enabled In Pwm Mode
50-MHz input clock and TnPWML = 0 (duty cycle would be 33% for the TnPWML = 1 configuration). For this example, the start value is GPTMTnILR=0xC350, and the match value is GPTMTnMATCHR=0x411A. SWRU543 – January 2019 General-Purpose Timers Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 314 GPTM Timer A Value (GPTMTAV) register [15:0] • GPTM Timer B Value (GPTMTBV) register [15:0] • GPTM Timer A Match (GPTMTAMATCHR) register [15:0] • GPTM Timer B Match (GPTMTBMATCHR) register [15:0] General-Purpose Timers SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 315 GPTMTnILR and GPTMTnPR registers and the GPTMTnMATCHR and GPTMTnPMR registers equals the number of edge events to be counted. SWRU543 – January 2019 General-Purpose Timers Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 316 8. Load the GPTM Timer n Match (GPTMTnMATCHR) register with the match value. 9. Set the TnEN bit in the GPTM Control (GPTMCTL) register to enable the timer and begin generation of the output PWM signal. General-Purpose Timers SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 317: Timer Registers
GPTM Timer B Section 9.5.18 GPTMTAV GPTM Timer A Value Section 9.5.19 GPTMTBV GPTM Timer B Value Section 9.5.20 GPTMDMAEV GPTM DMA Event Section 9.5.21 SWRU543 – January 2019 General-Purpose Timers Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 318: Gptmcfg Register
4h = For a 16/32-bit timer, this value selects the 16-bit timer configuration. The function is controlled by bits 1:0 of GPTMTAMR and GPTMTBMR. 5h - 7h = Reserved General-Purpose Timers SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 319: Gptmtamr Register
CAEDMAEN bit in the GPTMDMAEV register, respectively. This bit is only valid in PWM mode. 0h = Capture event interrupt is disabled. 1h = Capture event interrupt is enabled. SWRU543 – January 2019 General-Purpose Timers Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 320 2:0 in the GPTMCFG register. 0h = Reserved 1h = One-shot timer mode 2h = Periodic timer mode 3h = Capture mode General-Purpose Timers SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 321: Gptmtbmr Register
CBEDMAEN bit in the GPTMDMAEV register, respectively. This bit is only valid in PWM mode. 0h = Capture event interrupt is disabled. 1h = Capture event is enabled. SWRU543 – January 2019 General-Purpose Timers Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 322 2:0 in the GPTMCFG register. 0h = Reserved 1h = One-shot timer mode 2h = Periodic timer mode 3h = Capture mode General-Purpose Timers SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 323: Gptmctl Register
TAPWML GPTM Timer A PWM Output Level. The TAPWML values are defined as follows: 0h = Output is unaffected. 1h = Output is inverted. RESERVED SWRU543 – January 2019 General-Purpose Timers Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 324 0h = Timer A is disabled. 1h = Timer A is enabled and begins counting or the capture logic is enabled based on the GPTMCFG register. General-Purpose Timers SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 325: Gptmimr Register
DMAAIM GPTM Timer A DMA Done Interrupt Mask. The DMAAIM values are defined as follows: 0h = Interrupt is disabled. 1h = Interrupt is enabled. SWRU543 – January 2019 General-Purpose Timers Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 326 1h = Interrupt is enabled. TATOIM GPTM Timer A Time-Out Interrupt Mask. The TATOIM values are defined as follows: 0h = Interrupt is disabled. 1h = Interrupt is enabled. General-Purpose Timers SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 327: Gptmris Register
GPTM Timer A DMA Done Raw Interrupt Status 0h = The Timer A DMA transfer has not completed. 1h = The Timer A DMA transfer has completed. SWRU543 – January 2019 General-Purpose Timers Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 328 1h = Timer A has timed out. This interrupt is asserted when a one- shot or periodic mode timer reaches its count limit (0 or the value loaded into GPTMTAILR, depending on the count direction). General-Purpose Timers SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 329: Gptmmis Register
0h = A Timer A mode match interrupt has not occurred or is masked. 1h = An unmasked Timer A mode match interrupt has occurred. RESERVED SWRU543 – January 2019 General-Purpose Timers Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 330 1 to the TATOCINT bit in the GPTMICR register. 0h = A Timer A time-out interrupt has not occurred or is masked. 1h = An unmasked Timer A time-out interrupt has occurred. General-Purpose Timers SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 331: Gptmicr Register
GPTM Timer A Capture Mode Match Interrupt Clear. Writing 1 to this bit clears the CAMRIS bit in the GPTMRIS register and the CAMMIS bit in the GPTMMIS register. SWRU543 – January 2019 General-Purpose Timers Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 332 GPTM Timer A Time-Out Raw Interrupt. Writing 1 to this bit clears the TATORIS bit in the GPTMRIS register and the TATOMIS bit in the GPTMMIS register. General-Purpose Timers SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 333: Gptmtailr Register
TAILR FFFFFFFFh GPTM Timer A Interval Load Register. Writing this field loads the counter for Timer A. A read returns the current value of GPTMTAILR. SWRU543 – January 2019 General-Purpose Timers Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 334: Gptmtbilr Register
Timer B. A read returns the current value of GPTMTBILR. When a 16/32-bit GPTM is in 32-bit mode, writes are ignored, and reads return the current value of GPTMTBILR. General-Purpose Timers SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 335: Gptmtamatchr Register
Table 9-19. GPTMTAMATCHR Register Field Descriptions Field Type Reset Description 31-0 TAMR FFFFFFFFh GPTM Timer A Match Register. This value is compared to the GPTMTAR register to determine match events. SWRU543 – January 2019 General-Purpose Timers Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 336: Gptmtbmatchr Register
Table 9-20. GPTMTBMATCHR Register Field Descriptions Field Type Reset Description 31-0 TBMR FFFFh GPTM Timer B Match Register. This value is compared to the GPTMTBR register to determine match events. General-Purpose Timers SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 337: Gptmtapr Register
GPTM Timer A Prescale. The register loads this value on a write. A read returns the current value of the register. For the 16/32-bit GPTM, this field contains the entire 8-bit prescaler. SWRU543 – January 2019 General-Purpose Timers Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 338: Gptmtbpr Register
GPTM Timer B Prescale. The register loads this value on a write. A read returns the current value of this register. For the 16/32-bit GPTM, this field contains the entire 8-bit prescaler. General-Purpose Timers SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 339: Gptmtapmr Register
GPTM Timer A Prescale Match. This value is used alongside GPTMTAMATCHR to detect timer match events while using a prescaler. For the 16/32-bit GPTM, this field contains the entire 8-bit prescaler match value. SWRU543 – January 2019 General-Purpose Timers Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 340: Gptmtbpmr Register
Reset Description 31-8 RESERVED TBPSMR GPTM Timer B Prescale Match. This value is used alongside GPTMTBMATCHR to detect timer match events while using a prescaler. General-Purpose Timers SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 341: Gptmtar Register
In the input edge- time mode, this register contains the time at which the last edge event took place. SWRU543 – January 2019 General-Purpose Timers Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 342: Gptmtbr Register
In the input edge- time mode, this register contains the time at which the last edge event took place. General-Purpose Timers SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 343: Gptmtav Register
Note: In 16-bit mode, only the lower 16 bits of the GPTMTAV register can be written with a new value. Writes to the prescaler bits have no effect. SWRU543 – January 2019 General-Purpose Timers Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 344: Gptmtbv Register
In 16-bit mode, only the lower 16 bits of the GPTMTBV register can be written with a new value. Writes to the prescaler bits have no effect. General-Purpose Timers SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 345: Gptmdmaev Register
Timer A dma_req signal is sent to the DMA when a RTC match has occurred. 0h = Timer A RTC match DMA trigger is disabled. 1h = Timer A RTC match DMA trigger is enabled. SWRU543 – January 2019 General-Purpose Timers Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 346: Gptmdmaev Register Field Descriptions
Timer A dma_req signal is sent to the DMA on a time-out event. 0h = Timer A time-out DMA trigger is disabled. 1h = Timer A time-out DMA trigger is enabled. General-Purpose Timers SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 347 SWRU543 – January 2019 Watchdog Timer ........................... Topic Page ......................10.1 Overview ..................10.2 Functional Description ..................10.3 WATCHDOG Registers ............10.4 MCU Watchdog Controller Usage Caveats SWRU543 – January 2019 Watchdog Timer Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 348: Wdt Module Block Diagram
32-Bit Down Counter WDTMIS 0x0000.0000 WDTLOCK System Clock WDTTEST Comparator WDTVALUE Identification Registers WDTPCellID0 WDTPeriphID0 WDTPeriphID4 WDTPCellID1 WDTPeriphID1 WDTPeriphID5 WDTPCellID2 WDTPeriphID2 WDTPeriphID6 WDTPCellID3 WDTPeriphID3 WDTPeriphID7 Watchdog Timer SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 349 WDT is not serviced often enough. The RESEN bit in the WDTCTL register can be set so that the system resets if the failure is not recoverable using the interrupt service routine (ISR). SWRU543 – January 2019 Watchdog Timer Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 350: Watchdog Registers
WDTICR Watchdog Interrupt Clear Section 10.3.4 WDTRIS Watchdog Raw Interrupt Status Section 10.3.5 418h WDTTEST Watchdog Test Section 10.3.6 C00h WDTLOCK Watchdog Lock Section 10.3.7 Watchdog Timer SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 351: Wdtload Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 10-2. WDTLOAD Register Field Descriptions Field Type Reset Description 31-0 WDTLOAD FFFFFFFFh Watchdog Load Value SWRU543 – January 2019 Watchdog Timer Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 352: Wdtvalue Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 10-3. WDTVALUE Register Field Descriptions Field Type Reset Description 31-0 WDTVALUE FFFFFFFFh Watchdog Value Current value of the 32-bit down counter Watchdog Timer SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 353: Wdtctl Register
0h = Interrupt event disabled (when this bit is set, it can only be cleared by a hardware reset). 1h = Interrupt event enabled. Once enabled, all writes are ignored. Setting this bit enables the WDT. SWRU543 – January 2019 Watchdog Timer Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 354: Wdticr Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 10-5. WDTICR Register Field Descriptions Field Type Reset Description 31-0 WDTINTCLR Watchdog Interrupt Clear Watchdog Timer SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 355: Wdtris Register
Reset Description 31-1 RESERVED WDTRIS Watchdog Raw Interrupt Status 0h = The watchdog has not timed out. 1h = A watchdog time-out event has occurred. SWRU543 – January 2019 Watchdog Timer Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 356: Wdttest Register
1h = If the microcontroller is stopped with a debugger, the watchdog timer stops counting. Once the microcontroller is restarted, the watchdog timer resumes counting. RESERVED Watchdog Timer SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 357: Wdtlock Register
Avoid writes to the WDTTEST register when the watchdog registers are locked. A read of this register returns the following values: 0h = Unlocked 1h = Locked SWRU543 – January 2019 Watchdog Timer Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 358 (RTC) timer. This ensures a complete system cleanup. NOTE: For CC3220 variants, this step is not needed because it is done by the MCU ROM bootloader. Watchdog Timer SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 359: Watchdog Flow Chart
MCU Watchdog Controller Usage Caveats www.ti.com Figure 10-9. Watchdog Flow Chart SWRU543 – January 2019 Watchdog Timer Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 360: System Watchdog Recovery Sequence
The sequence shown in Figure 10-10 should be integrated in the user application for a reliable recovery from the WDOG trigger: Figure 10-10. System Watchdog Recovery Sequence Watchdog Timer SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 361 1-Bit SD Interface .......... 11.4 Initialization and Configuration Using Peripheral APIs .................. 11.5 Performance and Testing ..................11.6 Peripheral Library APIs ................... 11.7 SD-HOST Registers SWRU543 – January 2019 SD Host Controller Interface Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 362 Support for a wide range of card clock frequency with odd and even clock ratio. Maximum frequency supported is 24 MHz. 11.3 1-Bit SD Interface Figure 11-1 shows a block diagram of the SDHost Controller Interface. SD Host Controller Interface SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 363: Sdhost Controller Interface Block Diagram
Data: Data is transferred from the SD host controller to the card, or from a card to the SD host controller, using the DATA line. • Busy: The data signal is maintained low by the card, as it programs the data received. SWRU543 – January 2019 SD Host Controller Interface Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 364 4. Soft reset and initialize the host controller: PRCMPeripheralReset(PRCM_SDHOST) SDHostInit(SDHOST_BASE) 5. Soft reset and initialize the host controller for 15-MHz card clocks: SDHostSetExpClk(SDHOST_BASE, PRCMPeripheralClockGet(PRCM_SDHOST), 15000000) SD Host Controller Interface SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 365 The command does not take any argument. For this the SendCmd() is invoked as follows: #define CMD_GO_IDLE_STATE SDHOST_CMD_0 SendCmd(CMD_GO_IDLE_STATE, 0) SWRU543 – January 2019 SD Host Controller Interface Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 366 // Response contains 32-bit OCR register SDHostRespGet(SDHOST_BASE,ulResp); }while(((ulResp[0] >> 31) == 0)); if(ulResp[0] & (1UL<<30)) CardAttrib->ulCapClass = CARD_CAP_CLASS_SDHC; else //It's a MMC or SD 1.x card SD Host Controller Interface SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 367 == 0) SendCmd(CMD_SEND_REL_ADDR,0); SDHostRespGet(SDHOST_BASE,ulResp); Fill in the RCA CardAttrib->ulRCA = (ulResp[0] >> 16); // Get tha card capacity CardAttrib->ullCapacity = CardCapacityGet(CardAttrib->ulRCA); // return status. SWRU543 – January 2019 SD Host Controller Interface Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 368 SendCmd(CMD_READ_SINGLE_BLK, ulBlockNo) == 0 ) // Read out the data. while(ulSize--) MAP_SDHostDataRead(SDHOST_BASE,((unsigned long *)pBuffer); pBuffer+=4; else // Retutn error return 1; // Return success return 0; SD Host Controller Interface SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 369: Card Types
Table 11-1: Table 11-1. Card Types Vendor Size Capacity Class Block Read/Write Comments Transcend SDSC Passed Transcend 16GB SDHC Passed Strontium SDSC Passed SWRU543 – January 2019 SD Host Controller Interface Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 370: Throughput Data
Description: This function resets the SD host command line. • Parameters: ulBase – Base address of the SD host module • Return: None SD Host Controller Interface SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 371 – SDHOST_INT_DTO: Data Timeout error interrupt – SDHOST_INT_DCRC: Data CRC error interrupt – SDHOST_INT_DEB: Data End Bit error – SDHOST_INT_CERR: Cart Status Error interrupt SWRU543 – January 2019 SD Host Controller Interface Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 372 SDHostSetExpClk(unsigned long ulBase, unsigned long ulSDHostClk, unsigned long ulCardClk) • Description: This function configures the SD host interface to supply the specified clock to the connected card. SD Host Controller Interface SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 373 – ulBase – Base address of the SD host module – pulData – Pointer to data word to be transferred • Return: Return true on success, false otherwise SWRU543 – January 2019 SD Host Controller Interface Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 374 – ulBase – Base address of the SD host module – pulData – Pointer to data word to be transferred • Return: None SD Host Controller Interface SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 375: Base Address Of Sd-Host (Also Referred As Mmchs)
SD System Control Section 11.7.13 230h MMCHS_STAT Interrupt Status Section 11.7.14 234h MMCHS_IE Interrupt SD Enable Section 11.7.15 238h MMCHS_ISE Interrupt Signal Enable Section 11.7.16 SWRU543 – January 2019 SD Host Controller Interface Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 376: Mmchs_Csre Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 11-5. MMCHS_CSRE Register Field Descriptions Field Type Reset Description 31-0 CSRE Card status response error SD Host Controller Interface SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 377: Mmchs_Con Register
MMCi.MMCHS_CMD register, the host controller performs a 'command completion signal disable' token (such as mmci_cmd line held to 0 during 47 cycles followed by a 1). SWRU543 – January 2019 SD Host Controller Interface Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 378: Mmchs_Con Register Field Descriptions
MMCi.MMCHS_STAT[0] CC bit can be polled. 0h = The host does not send an initialization sequence. 1h = The host sends an initialization sequence. RESERVED SD Host Controller Interface SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 379: Mmchs_Blk Register
1FFh = 511 bytes block length 200h = 512 bytes block length 3FFh = 1023 bytes block length 400h = 1024 bytes block length SWRU543 – January 2019 SD Host Controller Interface Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 380: Mmchs_Arg Register
Table 11-8. MMCHS_ARG Register Field Descriptions Field Type Reset Description 31-0 Command argument bits [31:0] For CMD52, ARG must be programmed with IO_RW_DIRECT[39:8]. Refer to SDIO specification. SD Host Controller Interface SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 381: Mmchs_Cmd Register
Command with no data transfer, but using busy signal on mmci_dat[0] Resume command 0h = Command with no data transfer 1h = Command with data transfer SWRU543 – January 2019 SD Host Controller Interface Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 382: Mmchs_Cmd Register Field Descriptions
DMA enable This bit is used to enable DMA mode for host data access. 0h = DMA mode disable 1h = DMA mode enable SD Host Controller Interface SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 383: Mmchs_Rsp10 Register
R1/R1b (normal response) /R3/R4/R5/R5b/R6 : Command Response [39:24] R2: Command Response [31:16] 15-0 RSP0 R1/R1b (normal response) /R3/R4/R5/R5b/R6 : Command Response [23:8] R2: Command Response [15:0] SWRU543 – January 2019 SD Host Controller Interface Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 384: Mmchs_Rsp32 Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 11-11. MMCHS_RSP32 Register Field Descriptions Field Type Reset Description 31-16 RSP3 R2: Command Response [63:48] 15-0 RSP2 R2: Command Response [47:32] SD Host Controller Interface SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 385: Mmchs_Rsp54 Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 11-12. MMCHS_RSP54 Register Field Descriptions Field Type Reset Description 31-16 RSP5 R2: Command Response [95:80] 15-0 RSP4 R2: Command Response [79:64] SWRU543 – January 2019 SD Host Controller Interface Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 386: Mmchs_Rsp76 Register
R1b (Auto CMD12 response): Command Response [39:24] R2: Command Response [127:112] 15-0 RSP6 R1b (Auto CMD12 response): Command Response [23:8] R2: Command Response [111:96] SD Host Controller Interface SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 387: Mmchs_Data Register
1 (MMCi.MMCHS_PSTATE[10] BWE bit), otherwise a bad access (MMCi.MMCHS_STAT[29] BADA bit) is signaled and the data is not written. SWRU543 – January 2019 SD Host Controller Interface Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 388: Mmchs_Pstate Register
0h = No valid data on the mmci_dat lines 1h = Read data transfer ongoing SD Host Controller Interface SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 389: Mmchs_Pstate Register Field Descriptions
1), this register is not automatically cleared. 0h = Issuing of command using mmci_cmd line is allowed 1h = Issuing of command using mmci_cmd line is not allowed SWRU543 – January 2019 SD Host Controller Interface Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 390: Mmchs_Hctl Register
6h = 3.0 V (typical) 7h = 3.3 V (typical) MMCHS2: This field must be set to 0x5 MMCHS3: This field must be set to 0x5 RESERVED SD Host Controller Interface SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 391: Mmchs_Sysctl Register
This reset affects the entire host controller except for the card detection circuit and capabilities registers. 0h = Reset completed 1h = Software reset for all the designs 23-20 RESERVED SWRU543 – January 2019 SD Host Controller Interface Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 392 0h = The internal clock is stopped (very low power state). 1h = The internal clock oscillates and can be automatically gated when MMCi.MMCHS_SYSCONFIG[0] AUTOIDLE bit is set to 1 (default value). SD Host Controller Interface SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 393: Mmchs_Stat Register
Read 0h = No error Write 0h = Status bit unchanged Read 1h = Card error Write 1h = Status is cleared 27-23 RESERVED SWRU543 – January 2019 SD Host Controller Interface Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 394: Mmchs_Stat Register Field Descriptions
5 clock cycles, the time-out is still detected at 64 clock cycles. Read 0h = No error Write 0h = Status bit unchanged Read 1h = Time-out Write 1h = Status is cleared SD Host Controller Interface SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 395 Read 0h = No transfer complete Write 0h = Status bit unchanged Read 1h = Data transfer complete Write 1h = Status is cleared SWRU543 – January 2019 SD Host Controller Interface Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 396 Read 0h = No command complete Write 0h = Status bit unchanged Read 1h = Command complete Write 1h = Status is cleared SD Host Controller Interface SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 397: Mmchs_Ie Register
1h = The data time-out detection is enabled. RESERVED CEB_ENABLE Command end bit error interrupt enable 0h = Masked 1h = Enabled SWRU543 – January 2019 SD Host Controller Interface Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 398 RESERVED TC_ENABLE Transfer completed interrupt enable 0h = Masked 1h = Enabled CC_ENABLE Command completed interrupt enable 0h = Masked 1h = Enabled SD Host Controller Interface SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 399: Mmchs_Ise Register
Data time-out error signal status enable 0h = Masked 1h = Enabled RESERVED CEB_SIGEN Command end bit error signal status enable 0h = Masked 1h = Enabled RESERVED SWRU543 – January 2019 SD Host Controller Interface Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 400 Transfer completed signal status enable 0h = Masked 1h = Enabled CC_SIGEN Command completed signal status enable 0h = Masked 1h = Enabled SD Host Controller Interface SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 401 ..................12.2 Functional Description ..................12.3 Programming Model ............12.4 Peripheral Library APIs for I2S Configuration ....................12.5 I2S Registers SWRU543 – January 2019 Inter-Integrated Sound (I2S) Multichannel Audio Serial Port Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 402: I2S Protocol
Figure 12-1 shows the I2S protocol. Figure 12-1. I2S Protocol Figure 12-2 is a functional diagram of the I2S module. Inter-Integrated Sound (I2S) Multichannel Audio Serial Port SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 403: I2S Module
24-MHz clock to the I2S module. The minimum frequency obtained by configuring this divider is (240000 kHz/1023.99) = 234.377 kHz. SWRU543 – January 2019 Inter-Integrated Sound (I2S) Multichannel Audio Serial Port Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 404: Logical Clock Path
BitClock = (44100 * 2 * 16) = 1411200 Hz 2. Basic initialization a. Enable the I2S module clock by invoking Inter-Integrated Sound (I2S) Multichannel Audio Serial Port SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 405 // Check if there was a receive interrupt; if so read the data from the rx buffer and acknowledge // the interrupt if(ulStatus &I2S_STS_RDATA) I2SDataGetNonBlocking( I2S_BASE, I2S_DATA_LINE_1, &ulDummy); I2SIntClear(I2S_BASE,I2S_STS_RDATA); SWRU543 – January 2019 Inter-Integrated Sound (I2S) Multichannel Audio Serial Port Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 406 — sets the inactive state of the data line This function configures and enables the serializer associated with the given data line in specified mode. Inter-Integrated Sound (I2S) Multichannel Audio Serial Port SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 407 The ulConfig parameter is the logical OR of two values: the slot size and the data read/write port select. SWRU543 – January 2019 Inter-Integrated Sound (I2S) Multichannel Audio Serial Port Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 408 This function gets data from the receive register for the specified data line. Returns: Returns 0 on success, –1 otherwise. Inter-Integrated Sound (I2S) Multichannel Audio Serial Port SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 409 I2S interrupts must be enabled using I2SIntEnable(). The interrupt handler must clear the interrupt source. See IntRegister() for information about registering interrupt handlers. Returns: None SWRU543 – January 2019 Inter-Integrated Sound (I2S) Multichannel Audio Serial Port Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 410 -I2S_STS_RLAST -I2S_STS_RSYNCERR -I2S_STS_ROVERN -I2S_STS_RDMA Returns: Returns the current interrupt status, enumerated as a bit field of the previously described values. Inter-Integrated Sound (I2S) Multichannel Audio Serial Port SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 411: Ulintflags Parameter
Receive start of frame interrupt enable bit I2S_INT_RDATA 0x00200000 Receive data ready interrupt enable bit I2S_INT_RSTAFRM 0x00800000 Receive start of frame interrupt enable bit I2S_INT_RDMA 0x40000000 SWRU543 – January 2019 Inter-Integrated Sound (I2S) Multichannel Audio Serial Port Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 412: Ulstatflags Parameter
XRSR to RBUF, but the former data in RBUF has not yet been read by the CPU or DMA. I2S_STS_RDMA 0x40000000 Inter-Integrated Sound (I2S) Multichannel Audio Serial Port SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 413 — the base address of the I2S module This function gets the number of 32-bit words currently in the RX FIFO. Returns: Returns RX FIFO status. SWRU543 – January 2019 Inter-Integrated Sound (I2S) Multichannel Audio Serial Port Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 414 — the base address of the I2S module This function gets the number of 32-bit words currently in the TX FIFO. Returns: Returns TX FIFO status. Inter-Integrated Sound (I2S) Multichannel Audio Serial Port SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 415: I2S Registers Accessed Through Peripheral Configuration Port
Writes to XRBUF originate from peripheral configuration port only when XBUSEL = 1 in XFMT. Reads from XRBUF originate on peripheral configuration port only when RBUSEL = 1 in RFMT. SWRU543 – January 2019 Inter-Integrated Sound (I2S) Multichannel Audio Serial Port Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 416: I2S Registers Accessed Through Dma Port
Section 12.5.2 WFIFOSTS Write FIFO status register RFIFOCTL Read FIFO control register Section 12.5.4 RFIFOSTS Read FIFO status register Section 12.5.5 Inter-Integrated Sound (I2S) Multichannel Audio Serial Port SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 417: Afiforev Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 12-6. AFIFOREV Register Field Descriptions Field Type Reset Description 31-0 Identifies revision of peripheral. SWRU543 – January 2019 Inter-Integrated Sound (I2S) Multichannel Audio Serial Port Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 418: Wfifoctl Register
1h = 1 word 2h = 2 words 3h - 10h = 3 to 16 words 11h - FFh = Reserved Inter-Integrated Sound (I2S) Multichannel Audio Serial Port SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 419: Pdir Register
Determines if ACLKR pin functions as an input or output. 0h = Pin functions as input. 1h = Pin functions as output. SWRU543 – January 2019 Inter-Integrated Sound (I2S) Multichannel Audio Serial Port Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 420 Determines if AXR[n] pin functions as an input or output. 0h = Pin functions as input. 1h = Pin functions as output. Inter-Integrated Sound (I2S) Multichannel Audio Serial Port SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 421: Rfifoctl Register
1h = 1 word 2h = 2 words 3h - 10h = 3 to 16 words 11h - FFh = Reserved SWRU543 – January 2019 Inter-Integrated Sound (I2S) Multichannel Audio Serial Port Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 422: Rfifosts Register
2h = 2 words currently in Read FIFO. 3h - 40h = 3 to 64 words currently in Read FIFO. 41h - FFh = Reserved Inter-Integrated Sound (I2S) Multichannel Audio Serial Port SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 423: Gblctl Register
Transmit TDM time slot begins at slot 0 after reset is released. SWRU543 – January 2019 Inter-Integrated Sound (I2S) Multichannel Audio Serial Port Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 424 0h = Receive clock divider is held in reset. When the clock divider is in reset, it passes through a divide-by-1 of its input. 1h = Receive clock divider is running. Inter-Integrated Sound (I2S) Multichannel Audio Serial Port SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 425: Rgblctl Register
RSMRST bit of GBLCTL. 0h = Receive state machine is held in reset. 1h = Receive state machine is released from reset. SWRU543 – January 2019 Inter-Integrated Sound (I2S) Multichannel Audio Serial Port Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 426 RCLKRST bit of GBLCTL. 0h = Receive clock divider is held in reset. 1h = Receive clock divider is running. Inter-Integrated Sound (I2S) Multichannel Audio Serial Port SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 427: Rmask Register
1h = Corresponding bit of receive data (after passing through reverse and rotate units) is returned to CPU or DMA. SWRU543 – January 2019 Inter-Integrated Sound (I2S) Multichannel Audio Serial Port Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 428: Rfmt Register
RBUF[n]) is used to pad the extra bits. This field only applies when RPAD = 2h. 0h - 1Fh = Reserved Inter-Integrated Sound (I2S) Multichannel Audio Serial Port SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 429 A value written to this field has no effect. If writing to this field, always write the default value for future device compatibility. SWRU543 – January 2019 Inter-Integrated Sound (I2S) Multichannel Audio Serial Port Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 430: Afsrctl Register
Receive frame sync polarity select bit. 0h = Reserved 1h = A falling edge on receive frame sync (AFSR) indicates the beginning of a frame. Inter-Integrated Sound (I2S) Multichannel Audio Serial Port SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 431: Rtdm Register
1h = Receive TDM time slot 0 is active. The receive serializer shifts in data during this slot. SWRU543 – January 2019 Inter-Integrated Sound (I2S) Multichannel Audio Serial Port Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 432: Rintctl Register
McASP receive interrupt (RINT). 1h = Interrupt is enabled. An unexpected receive frame sync interrupt generates a McASP receive interrupt (RINT). Inter-Integrated Sound (I2S) Multichannel Audio Serial Port SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 433 McASP receive interrupt (RINT). 1h = Interrupt is enabled. A receiver overrun interrupt generates a McASP receive interrupt (RINT). SWRU543 – January 2019 Inter-Integrated Sound (I2S) Multichannel Audio Serial Port Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 434: Rstat Register
1h = Data is transferred from XRSR to RBUF and ready to be serviced by the CPU or DMA. When RDATA is set, it always causes a DMA event (AREVT). Inter-Integrated Sound (I2S) Multichannel Audio Serial Port SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 435 This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect. 0h = Receiver overrun did not occur. 1h = Receiver overrun did occur. SWRU543 – January 2019 Inter-Integrated Sound (I2S) Multichannel Audio Serial Port Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 436: Rslot Register
RSLOTCNT Current receive time slot count. Legal values: 0 or 1 Inter-Integrated Sound (I2S) Multichannel Audio Serial Port SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 437: Revtctl Register
Receive data DMA request enable bit. If writing to this field, always write the default value of 0. 0h = Receive data DMA request is enabled. 1h = Reserved. SWRU543 – January 2019 Inter-Integrated Sound (I2S) Multichannel Audio Serial Port Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 438: Xgblctl Register
Receive frame sync generator reset enable bit. A read of this bit returns the RFRST bit value of GBLCTL. Writes have no effect. Inter-Integrated Sound (I2S) Multichannel Audio Serial Port SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 439 Receive clock divider reset enable bit. A read of this bit returns the RCLKRST bit value of GBLCTL. Writes have no effect. SWRU543 – January 2019 Inter-Integrated Sound (I2S) Multichannel Audio Serial Port Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 440: Xmask Register
McASP in place of the original bit. 1h = Corresponding bit of transmit data (before passing through reverse and rotate units) is transmitted out the McASP. Inter-Integrated Sound (I2S) Multichannel Audio Serial Port SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 441: Xfmt Register
Ah = Reserved Bh = Slot size is 24 bits Ch = Reserved Dh = Reserved Eh = Reserved Fh = Reserved SWRU543 – January 2019 Inter-Integrated Sound (I2S) Multichannel Audio Serial Port Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 442 4h = Rotate right by 16 bit positions. 5h = Reserved 6h = Rotate right by 24 bit positions. 7h = Reserved Inter-Integrated Sound (I2S) Multichannel Audio Serial Port SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 443: Afsxctl Register
Transmit frame sync polarity select bit. 0h = Reserved 1h = A falling edge on transmit frame sync (AFSX) indicates the beginning of a frame. SWRU543 – January 2019 Inter-Integrated Sound (I2S) Multichannel Audio Serial Port Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 444: Aclkxctl Register
Transmit bit clock divide ratio bits determine the divide-down ratio from AHCLKX to ACLKX. 0h = Divide-by-1 1h = Divide-by-2 2h - 1Fh = Divide-by-3 to divide-by-32 Inter-Integrated Sound (I2S) Multichannel Audio Serial Port SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 445: Ahclkxctl Register
Transmit high-frequency clock divide ratio bits determine the divide- down ratio from AUXCLK to AHCLKX. 0h = Divide-by-1 1h = Divide-by-2 2h - FFFh = Divide-by-3 to divide-by-4096 SWRU543 – January 2019 Inter-Integrated Sound (I2S) Multichannel Audio Serial Port Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 446: Xtdm Register
1h = Transmit TDM time slot n is active. The transmit serializer shifts out data during this slot according to the serializer control register (SRCTL). Inter-Integrated Sound (I2S) Multichannel Audio Serial Port SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 447: Xintctl Register
McASP transmit interrupt (XINT). 1h = Interrupt is enabled. An unexpected transmit frame sync interrupt generates a McASP transmit interrupt (XINT). SWRU543 – January 2019 Inter-Integrated Sound (I2S) Multichannel Audio Serial Port Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 448 McASP transmit interrupt (XINT). 1h = Interrupt is enabled. A transmitter underrun interrupt generates a McASP transmit interrupt (XINT). Inter-Integrated Sound (I2S) Multichannel Audio Serial Port SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 449: Xstat Register
0h = Current slot is not the last slot in a frame. 1h = Current slot is the last slot in a frame. XDATA is also set. SWRU543 – January 2019 Inter-Integrated Sound (I2S) Multichannel Audio Serial Port Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 450 Writing a 0 has no effect. 0h = Transmitter underrun did not occur. 1h = Transmitter underrun did occur. Inter-Integrated Sound (I2S) Multichannel Audio Serial Port SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 451: Xslot Register
XSLOTCNT 17Fh Current transmit time slot count. Legal values: 0 to 1 SWRU543 – January 2019 Inter-Integrated Sound (I2S) Multichannel Audio Serial Port Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 452: Xevtctl Register
Transmit data DMA request enable bit. If writing to this field, always write the default value of 0. 0h = Transmit data DMA request is enabled. 1h = Reserved. Inter-Integrated Sound (I2S) Multichannel Audio Serial Port SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 453: Srctln Registers
1h = Transmit buffer (XBUF) is empty and must be written before the start of the next time slot or a transmit underrun occurs. SWRU543 – January 2019 Inter-Integrated Sound (I2S) Multichannel Audio Serial Port Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 454 Serializer mode bit. 0h = Serializer is inactive. 1h = Serializer is transmitter. 2h = Serializer is receiver. 3h = Reserved Inter-Integrated Sound (I2S) Multichannel Audio Serial Port SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 455: Xbufn Registers
The XBUF can be accessed through the peripheral configuration port (see ) or through the DMA port (see ). SWRU543 – January 2019 Inter-Integrated Sound (I2S) Multichannel Audio Serial Port Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 456: Rbufn Registers
The RBUF can be accessed through the peripheral configuration port (see ) or through the DMA port (see ). Inter-Integrated Sound (I2S) Multichannel Audio Serial Port SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 457 Key Features ..................13.3 ADC Register Mapping ................... 13.4 ADC_MODULE Registers ................13.5 Initialization and Configuration ............13.6 Peripheral Library APIs for ADC Operation SWRU543 – January 2019 Analog-to-Digital Converter (ADC) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 458: Architecture Of The Adc Module In Cc32Xx
Figure 13-1 shows the architecture of the ADC module in the CC32xx. Figure 13-1. Architecture of the ADC Module in CC32xx Analog-to-Digital Converter (ADC) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 459: Operation Of The Adc
CC32xx SoC. Register bits and functions related to these internal channels are marked as reserved in the register description. These bits must not be modified by application code to ensure proper functioning of the system. SWRU543 – January 2019 Analog-to-Digital Converter (ADC) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 460: Adc_Module Registers
ADC Enable Register for Application Channels Section 13.4.1.21 13.4.1 ADC Register Description The remainder of this section lists and describes the ADC registers, in numerical order by address offset. Analog-to-Digital Converter (ADC) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 461: Adc_Ctrl Register
RESERVED R-0h RESERVED ADC_EN_APP R-0h R/W-0h Table 13-3. ADC_CTRL Register Field Descriptions Field Type Reset Description 31-1 RESERVED ADC_EN_APPS ADC enable for application processor SWRU543 – January 2019 Analog-to-Digital Converter (ADC) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 462: Adc_Ch0_Irq_En Register
Bit 2: when 1 -> enable FIFO underflow interrupt Bit 1: when 1 -> enable FIFO empty interrupt Bit 0: when 1 -> enable FIFO full interrupt Analog-to-Digital Converter (ADC) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 463: Adc_Ch2_Irq_En Register
Bit 2: when 1 -> enable FIFO underflow interrupt Bit 1: when 1 -> enable FIFO empty interrupt Bit 0: when 1 -> enable FIFO full interrupt SWRU543 – January 2019 Analog-to-Digital Converter (ADC) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 464: Adc_Ch4_Irq_En Register
Bit 2: when 1 -> enable FIFO underflow interrupt Bit 1: when 1 -> enable FIFO empty interrupt Bit 0: when 1 -> enable FIFO full interrupt Analog-to-Digital Converter (ADC) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 465: Adc_Ch6_Irq_En Register
Bit 2: when 1 -> enable FIFO underflow interrupt Bit 1: when 1 -> enable FIFO empty interrupt Bit 0: when 1 -> enable FIFO full interrupt SWRU543 – January 2019 Analog-to-Digital Converter (ADC) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 466: Adc_Ch0_Irq_Status Register
Bit 1: when value 1 is written -> Clears FIFO empty interrupt status in the next cycle. Bit 0: when value 1 is written -> Clears FIFO full interrupt status in the next cycle. Analog-to-Digital Converter (ADC) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 467: Adc_Ch2_Irq_Status Register
Bit 1: when value 1 is written -> Clears FIFO empty interrupt status in the next cycle. Bit 0: when value 1 is written -> Clears FIFO full interrupt status in the next cycle. SWRU543 – January 2019 Analog-to-Digital Converter (ADC) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 468: Adc_Ch4_Irq_Status Register
Bit 1: when value 1 is written -> Clears FIFO empty interrupt status in the next cycle. Bit 0: when value 1 is written -> Clears FIFO full interrupt status in the next cycle. Analog-to-Digital Converter (ADC) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 469: Adc_Ch6_Irq_Status Register
Bit 1: when value 1 is written -> Clears FIFO empty interrupt status in the next cycle. Bit 0: when value 1 is written -> Clears FIFO full interrupt status in the next cycle. SWRU543 – January 2019 Analog-to-Digital Converter (ADC) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 470: Adc_Dma_Mode_En Register
Bit 6: Channel 6 DMA mode enable Bit 7: Reserved for internal channel 0h = Only the interrupt mode is enabled. 1h = Respective ADC channel is enabled for DMA. Analog-to-Digital Converter (ADC) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 471: Adc_Timer_Configuration Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED TIMERCURRENTCOUNT R-0h R-0h Table 13-14. ADC_TIMER_CURRENT_COUNT Register Field Descriptions Field Type Reset Description 31-17 RESERVED 16-0 TIMERCURRENTCOUNT Timer count configuration SWRU543 – January 2019 Analog-to-Digital Converter (ADC) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 472: Channel0Fifodata Register
Read to this register returns ADC data, along with timestamp information in the following format: [1:0] : Reserved [13:2] : ADC sample bits [30:14]: Timestamp per ADC sample [31] : Reserved Analog-to-Digital Converter (ADC) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 473: Channel4Fifodata Register
Read to this register returns ADC data, along with time stamp information in the following format: [1:0] : Reserved [13:2] : ADC sample bits [30:14]: Timestamp per ADC sample [31] : Reserved SWRU543 – January 2019 Analog-to-Digital Converter (ADC) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 474: Adc_Ch0_Fifo_Lvl Register
Reset Description 31-3 RESERVED ADC_CHANNEL0_FIFO_ This register shows the current FIFO level. FIFO is 4 words wide. Possible supported levels are 0x0 to 0x4. Analog-to-Digital Converter (ADC) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 475: Adc_Ch2_Fifo_Lvl Register
Reset Description 31-3 RESERVED ADC_CHANNEL2_FIFO_ This register shows the current FIFO level. FIFO is 4 words wide. Possible supported levels are 0x0 to 0x4. SWRU543 – January 2019 Analog-to-Digital Converter (ADC) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 476: Adc_Ch4_Fifo_Lvl Register
Reset Description 31-3 RESERVED ADC_CHANNEL4_FIFO_ This register shows the current FIFO level. FIFO is 4 words wide. Possible supported levels are 0x0 to 0x4. Analog-to-Digital Converter (ADC) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 477: Adc_Ch6_Fifo_Lvl Register
Reset Description 31-3 RESERVED ADC_CHANNEL6_FIFO_ This register shows the current FIFO level. FIFO is 4 words wide. Possible supported levels are 0x0 to 0x4. SWRU543 – January 2019 Analog-to-Digital Converter (ADC) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 478: Adc_Ch_Enable Register
Bit2: 1 connects channel 2 to pin 58 (ADC_CH1) Bit3: 1 connects channel 4 to pin 59 (ADC_CH2) Bit4: 1 connects channel 6 to pin 60 (ADC_CH3) RESERVED Analog-to-Digital Converter (ADC) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 479: Ulchannel Tags
Table 13-24. ulChannel Tags Value ADC_CH_0 0x00000000 ADC_CH_1 0x00000008 ADC_CH_2 0x00000010 ADC_CH_3 0x00000018 SWRU543 – January 2019 Analog-to-Digital Converter (ADC) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 480: Ulintflags Tags
One of the valid ADC channels This function enables specified ADC channel and configures the pin as an analog pin. Returns: • None Analog-to-Digital Converter (ADC) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 481 Returns one data sample from the channel FIFO. 13.6.4.3 void ADCDMAEnable (unsigned long ulBase, unsigned long ulChannel) Enables the ADC DMA operation for a specified channel. Parameters: SWRU543 – January 2019 Analog-to-Digital Converter (ADC) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 482 ADC_CH_2 for channel 2 • ADC_CH_3 for channel 3 The ulIntFlags parameter is the logical OR of any of the following: • ADC_DMA_DONE for DMA done Analog-to-Digital Converter (ADC) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 483 The ulChannel parameter should be one of the following: • ADC_CH_0 for channel 0 • ADC_CH_1 for channel 1 • ADC_CH_2 for channel 2 • ADC_CH_3 for channel 3 Returns: • None SWRU543 – January 2019 Analog-to-Digital Converter (ADC) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 484 This function clears an individual interrupt source for the specified ADC channel. The ulChannel parameter should be as explained in ADCIntEnable(). Returns: • None Analog-to-Digital Converter (ADC) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 485 This function resets the 17-bit ADC internal timer. Returns: • None 13.6.6.5 unsigned long ADCTimerValueGet (unsigned long ulBase) Gets the current value of ADC internal timer. Parameters: SWRU543 – January 2019 Analog-to-Digital Converter (ADC) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 486 Base address of the ADC This function gets the current value of the 17-bit ADC internal timer. Returns: • Returns the current value of the ADC internal timer. Analog-to-Digital Converter (ADC) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 487 Functional Description ..................14.4 Programming Model ..................... 14.5 Interrupt Handling ..................... 14.6 Camera Registers ..................14.7 Peripheral Library APIs .................... 14.8 Developer’s Guide SWRU543 – January 2019 Parallel Camera Interface Module Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 488: Camera Module Interfaces
CC32xx device. Figure 14-1. Camera Module Interfaces 14.2 Image Sensor Interface Table 14-1 lists the image sensor interface signals. Parallel Camera Interface Module SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 489: Synchronization Signals And Frame Timing
The acquisition can start either on a beginning of a new frame (CAM_P_VS inactive and then active) or immediately in function of the CC_CTRL.NOBT_SYNCHRO register bit. Set CC_CTRL.NOBT_SYNCHRO to 1 to ensure a clean acquisition of the frame. SWRU543 – January 2019 Parallel Camera Interface Module Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 490: Cam_P_Hs Toggles Between Pixels In Decimation
The camera core module supports decimation from the image sensor where CAM_P_HS toggles between pixels (see Figure 14-5). Figure 14-5. CAM_P_HS Toggles Between Pixels in Decimation Parallel Camera Interface Module SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 491: Parallel Camera Interface State Machine
Image data is stored differently in the FIFO, depending on the setting of the PAR_ORDERCAM bit, as shown in Figure 14-7. Figure 14-7. FIFO Image Data Format SWRU543 – January 2019 Parallel Camera Interface Module Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 492 CAM_XCLK is not used by the camera core module; it is routed to the chip pin. Table 14-2 lists the ratio of the XCLK frequency generator. Parallel Camera Interface Module SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 493: Ratio Of The Xclk Frequency Generator
Figure 14-8 shows the DMA assertion and deassertion, assuming a FIFO threshold of 8, plus some remaining data to end the frame acquisition. SWRU543 – January 2019 Parallel Camera Interface Module Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 494: Assertion And Deassertion Of The Dma Request Signal
NOBT_SYNCHRO to 1 when CC_EN is set to 1, to start the acquisition. If software only acquires one frame acquisition, use the CC_ONE_SHOT register bit (in this case, the module is automatically disabled at the end of the frame). Parallel Camera Interface Module SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 495: 14.5 Interrupt Handling
4. Set the CC_CTRL.CC_EN bit to 1, to re-enable the data flow from the image sensor. If an underflow occurs, the entire data flow path must be reset to restart cleanly. SWRU543 – January 2019 Parallel Camera Interface Module Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 496: Camera Registers
Section 14.6.5 CC_CTRL_DMA Control DMA Register Section 14.6.6 CC_CTRL_XCLK External Clock Control Register Section 14.6.7 4Ch to 1FCh CC_FIFODATA FIFO Data Register Section 14.6.8 Parallel Camera Interface Module SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 497: Cc_Sysconfig Register
Internal OCP clock gating strategy 0h = OCP clock is free-running 1h = Automatic OCP clock gating strategy is applied, based on the OCP interface activity SWRU543 – January 2019 Parallel Camera Interface Module Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 498: Cc_Sysstatus Register
Table 14-5. CC_SYSSTATUS Register Field Descriptions Field Type Reset Description 31-1 RESERVED ResetDone Internal Reset Monitoring 0h = Internal module reset is ongoing. 1h = Reset completed Parallel Camera Interface Module SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 499: Cc_Irqstatus Register
0h (W) = Event status bit unchanged 0h (R) = Event false 1h (W) = Event status bit is reset 1h (R) = Event is true ("pending") SWRU543 – January 2019 Parallel Camera Interface Module Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 500: Cc_Irqstatus Register Field Descriptions
0h (W) = Event status bit unchanged 0h (R) = Event false 1h (W) = Event status bit is reset 1h (R) = Event is true ("pending") Parallel Camera Interface Module SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 501: Cc_Irqenable Register
1h = Event generates an interrupt when it occurs SSC_ERR_IRQ_EN False Synchronization Code Interrupt Enable 0h = Event is masked 1h = Event generates an interrupt when it occurs SWRU543 – January 2019 Parallel Camera Interface Module Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 502: Cc_Irqenable Register Field Descriptions
1h = Event generates an interrupt when it occurs FIFO_UF_IRQ_EN FIFO Underflow Interrupt Enable 0h = Event is masked 1h = Event generates an interrupt when it occurs Parallel Camera Interface Module SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 503: Cc_Ctrl Register
By writing 0 to this field, the module is disabled at the end of the frame if CC_FRAME_TRIG = 1, and is disabled immediately if CC_FRAME_TRIG = 0. 15-14 RESERVED SWRU543 – January 2019 Parallel Camera Interface Module Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 504 010h = Parallel NOBT 12-bit 011h = Reserved 100h = Parallel BT 8-bit 101h = Parallel BT 10-bit 110h = Reserved 111h = FIFO test mode. Parallel Camera Interface Module SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 505: Cc_Ctrl_Dma Register
00000000h = Threshold set to 1 00000001h = Threshold set to 2 01111111h = Threshold set to 128 SWRU543 – January 2019 Parallel Camera Interface Module Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 506: Cc_Ctrl_Xclk Register
00000001h = CAM_XCLK Stable high level from 2 to 30 = CAM_XCLK = CAM_MCLK / XCLK DIV 00011111h = Bypass - CAM_XCLK = CAM_MCLK Parallel Camera Interface Module SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 507: Cc_Fifodata Register
Table 14-11. CC_FIFODATA Register Field Descriptions Field Type Reset Description 31-0 FIFO_DATA Reads or writes the 32-bit word from or into the FIFO. SWRU543 – January 2019 Parallel Camera Interface Module Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 508: 14.7 Peripheral Library Apis
– CAM_XCLK_STABLE_LO XCLK line will be pulled low. – CAM_XCLK_STABLE_HI XCLK line will be pulled high. – CAM_XCLK_DIV_BYPASS XCLK divider is in bypass mode. Parallel Camera Interface Module SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 509 – CAM_INT_FIFO_FULL – FIFO full interrupt – CAM_INT_FIFO_THR – FIFO reached threshold interrupt – CAM_INT_FIFO_OF – FIFO overflow interrupt – CAN_INT_FIFO_UR – FIFO underflow interrupt • Return: None SWRU543 – January 2019 Parallel Camera Interface Module Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 510 – ulBase – Base address of the camera module – pBuffer – Pointer to the read buffer – ucSize – Size of data to be read • Return: None Parallel Camera Interface Module SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 511: 14.8 Developer's Guide
The ping-pong transfer can be set up by using the peripheral driver API DMASetupTransfer. The following code shows how this API could be used: SWRU543 – January 2019 Parallel Camera Interface Module Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 512 /* Setup the buffer for the next ping/pong */<data_buffer> += <total_dma_elements>; if (<on an error>) /* Disable DMA and mask ‘CAM_THRESHHOLD_DMA_DONE’ */ UDMAStopTransfer(UDMA_CH22_CAMERA);<write_register>(0x44026090) |= 1 << 8; Parallel Camera Interface Module SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 513 Description: Receives a byte that has been sent to the I2C master. • Parameters: – ui32Base – the base address of the I2C master module SWRU543 – January 2019 Parallel Camera Interface Module Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 514 – ui32Base – the base address of the I2C master module – bMasked – False if the raw interrupt status is requested, and True if the masked interrupt status is requested Parallel Camera Interface Module SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 515 15.2 Power Management Control Architecture ...................... 15.3 PRCM APIs ..................... 15.4 Peripheral Macros ................. 15.5 Power Management Framework ....................15.6 PRCM Registers SWRU543 – January 2019 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 516 – PMU state transitions are initiated by control signals from the PRCM. ® See the CC3235S and CC3235SF SimpleLink™ Wi-Fi , Dual-Band, Single-Chip Solution data sheet the chip wake-up sequence and timing parameters. Power, Reset, and Clock Management SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 517: Power Management Unit Configuration
PMU, including the hibernate controller, into a reset state where V < supply is typically 1.4 V and varies with temperature. blackout blackout SWRU543 – January 2019 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 518 – A brief hibernation may also be used by software to implement a full system reboot as part of an over-the-air (OTA) software upgrade, or to restore the system to a ensured clean state following a watchdog reset. Power, Reset, and Clock Management SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 519: Sleep Modes
This approach insulates the user from the real-time complexities of a multiprocessor system; it improves robustness by eliminating race conditions and simplifies the application development process. SWRU543 – January 2019 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 520: Possible Pm State Combinations Of Application Processor And Network Subsystem (Nwp+Wlan)
CC32xx. The software interface to power management is limited to a subset of GPRCM registers, which are accessed through a set of easy-to-use API functions described in Section 15.3. Power, Reset, and Clock Management SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 521: Power Management Control Architecture In Cc32Xx
Power Management Control Architecture www.ti.com Figure 15-3. Power Management Control Architecture in CC32xx SWRU543 – January 2019 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 522 Description: This function performs a software reset of the specified peripheral. Parameter: ulPeripheral – A valid peripheral macro (see Section 15.4) Return: None Power, Reset, and Clock Management SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 523 – PRCM_RUN_MODE_CLK: Gates clock to the peripheral during run mode. – PRCM_SLP_MODE_CLK: Keeps the clock gated during sleep. – PRCM_DSLP_MODE_CLK: Keeps the clock gated during deep sleep. Return: None SWRU543 – January 2019 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 524 PRCMSleepEnter() Description: Enter sleep power mode by invoking a WFI instruction. Parameter: None Return: None Power, Reset, and Clock Management SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 525 The timer is started only when the system enters LPDS. Parameter: ulTicks: Wake-up interval in 32.768-kHz ticks Return: None SWRU543 – January 2019 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 526 ROM bootloader upon wakeup due to configured wake sources, which include the following: • Slow clock counter – Always-on 32.768-kHz counter • HIB wake-up GPIOs – Six selected GPIOs Power, Reset, and Clock Management SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 527 – PRCM_LPDS_GPIO13: GPIO13 – PRCM_LPDS_GPIO17: GPIO17 – PRCM_LPDS_GPIO11: GPIO11 – PRCM_LPDS_GPIO24: GPIO24 • ulType: Event Type. ulType can be one of the following: SWRU543 – January 2019 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 528 PRCMSlowClkCtrMatchSet(unsigned long long ullTicks) Description: This function sets the match value of the slow clock triggered interrupt. Parameter: ullTicks: 48-bit match value Return: None Power, Reset, and Clock Management SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 529: Peripheral Macro Table
Section 15.6.7 SDIOMSWRST Section 15.6.8 APSPICLKCFG Section 15.6.9 APSPICLKEN Section 15.6.10 APSPISWRST Section 15.6.11 DMACLKEN Section 15.6.12 DMASWRST Section 15.6.13 GPIO0CLKEN Section 15.6.14 SWRU543 – January 2019 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 530 Section 15.6.45 110h SLPWAKEEN Section 15.6.46 114h SLPTMRCFG Section 15.6.47 118h WAKENWP Section 15.6.48 120h RCM_IS Section 15.6.49 124h RCM_IEN Section 15.6.50 Power, Reset, and Clock Management SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 531: Camclkcfg Register
000h = 1 001h = 2 010h = 3 011h = 4 100h = 5 101h = 6 110h = 7 111h = 8 SWRU543 – January 2019 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 532: Camclken Register
1h = Enable camera clock during sleep mode RUNCLKEN CAMERA_RUN_CLK_ENABLE 0h = Disable camera clock during run mode 1h = Enable camera clock during run mode Power, Reset, and Clock Management SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 533: Camswrst Register
0h = Camera clocks/resets are disabled 1h = Camera clocks/resets are enabled SWRST CAMERA_SOFT_RESET 0h = Deassert reset for Camera-core 1h = Assert reset for Camera-core SWRU543 – January 2019 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 534: Mcaspclken Register
1h = Enable MCASP clock during sleep mode RUNCLKEN MCASP_RUN_CLK_ENABLE 0h = Disable MCASP clock during run mode 1h = Enable MCASP clock during run mode Power, Reset, and Clock Management SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 535: Mcaspswrst Register
0h = MCASP Clocks/resets are disabled 1h = MCASP Clocks/resets are enabled SWRST MCASP_SOFT_RESET 0h = Deassert reset for MCASP-core 1h = Assert reset for MCASP-core SWRU543 – January 2019 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 536: Sdiomclkcfg Register
000h = 1 001h = 2 010h = 3 011h = 4 100h = 5 101h = 6 110h = 7 111h = 8 Power, Reset, and Clock Management SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 537: Sdiomclken Register
1h = Enable MMCHS clock during sleep mode RUNCLKEN MMCHS_RUN_CLK_ENABLE 0h = Disable MMCHS clock during run mode 1h = Enable MMCHS clock during run mode SWRU543 – January 2019 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 538: Sdiomswrst Register
1h = MMCHS clocks and resets are enabled SWRST MMCHS_SOFT_RESET 0h = Deassert reset for MMCHS-core 1h = Assert reset for MMCHS-core Power, Reset, and Clock Management SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 539: Apspiclkcfg Register
000h = 1 001h = 2 010h = 3 011h = 4 100h = 5 101h = 6 110h = 7 111h = 8 SWRU543 – January 2019 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 540: Apspiclken Register
1h = Enable MCSPI_A1 clock during sleep mode RUNCLKEN MCSPI_A1_RUN_CLK_ENABLE 0h = Disable MCSPI_A1 clock during run mode 1h = Enable MCSPI_A1 clock during run mode Power, Reset, and Clock Management SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 541: Apspiswrst Register
1h = MCSPI_A1 clocks and resets are enabled SWRST MCSPI_A1_SOFT_RESET 0h = Deassert reset for MCSPI_A1-core 1h = Assert reset for MCSPI_A1-core SWRU543 – January 2019 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 542: Dmaclken Register
1h = Enable UDMA_A clock during sleep mode RUNCLKEN UDMA_A_RUN_CLK_ENABLE 0h = Disable UDMA_A clock during run mode 1h = Enable UDMA_A clock during run mode Power, Reset, and Clock Management SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 543: Dmaswrst Register
1h = UDMA_A clocks and resets are enabled SWRST UDMA_A_SOFT_RESET 0h = Deassert reset for DMA_A 1h = Assert reset for DMA_A SWRU543 – January 2019 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 544: Gpio0Clken Register
1h = Enable GPIO_A clock during sleep mode RUNCLKEN GPIO_A_RUN_CLK_ENABLE 0h = Disable GPIO_A clock during run mode 1h = Enable GPIO_A clock during run mode Power, Reset, and Clock Management SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 545: Gpio0Swrst Register
1h = GPIO_A clocks and resets are enabled SWRST GPIO_A_SOFT_RESET 0h = Deassert reset for GPIO_A 1h = Assert reset for GPIO_A SWRU543 – January 2019 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 546: Gpio1Clken Register
1h = Enable GPIO_B clock during sleep mode RUNCLKEN GPIO_B_RUN_CLK_ENABLE 0h = Disable GPIO_B clock during run mode 1h = Enable GPIO_B clock during run mode Power, Reset, and Clock Management SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 547: Gpio1Swrst Register
1h = GPIO_B clocks and resets are enabled SWRST GPIO_B_SOFT_RESET 0h = Deassert reset for GPIO_B 1h = Assert reset for GPIO_B SWRU543 – January 2019 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 548: Gpio2Clken Register
1h = Enable GPIO_C clock during sleep mode RUNCLKEN GPIO_C_RUN_CLK_ENABLE 0h = Disable GPIO_C clock during run mode 1h = Enable GPIO_C clock during run mode Power, Reset, and Clock Management SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 549: Gpio2Swrst Register
1h = GPIO_C clocks and resets are enabled SWRST GPIO_C_SOFT_RESET 0h = Deassert reset for GPIO_C 1h = Assert reset for GPIO_C SWRU543 – January 2019 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 550: Gpio3Clken Register
1h = Enable GPIO_D clock during sleep mode RUNCLKEN GPIO_D_RUN_CLK_ENABLE 0h = Disable GPIO_D clock during run mode 1h = Enable GPIO_D clock during run mode Power, Reset, and Clock Management SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 551: Gpio3Swrst Register
1h = GPIO_D clocks and resets are enabled SWRST GPIO_D_SOFT_RESET 0h = Deassert reset for GPIO_D 1h = Assert reset for GPIO_D SWRU543 – January 2019 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 552: Gpio4Clken Register
1h = Enable GPIO_E clock during sleep mode RUNCLKEN GPIO_E_RUN_CLK_ENABLE 0h = Disable GPIO_E clock during run mode 1h = Enable GPIO_E clock during run mode Power, Reset, and Clock Management SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 553: Gpio4Swrst Register
1h = GPIO_E clocks and resets are enabled SWRST GPIO_E_SOFT_RESET 0h = Deassert reset for GPIO_E 1h = Assert reset for GPIO_E SWRU543 – January 2019 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 554: Wdtclken Register
1h = Enable WDOG_A clock during sleep mode RUNCLKEN WDOG_A_RUN_CLK_ENABLE 0h = Disable WDOG_A clock during run mode 1h = Enable WDOG_A clock during run mode Power, Reset, and Clock Management SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 555: Wdtswrst Register
1h = WDOG_A clocks and resets are enabled SWRST WDOG_A_SOFT_RESET 0h = Deassert reset for WDOG_A 1h = Assert reset for WDOG_A SWRU543 – January 2019 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 556: Uart0Clken Register
1h = Enable UART_A0 clock during sleep mode UART0RCLKEN UART_A0_RUN_CLK_ENABLE 0h = Disable UART_A0 clock during run mode 1h = Enable UART_A0 clock during run mode Power, Reset, and Clock Management SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 557: Uart0Swrst Register
1h = UART_A0 clocks and resets are enabled SWRST UART_A0_SOFT_RESET 0h = Deassert reset for UART_A0 1h = Assert reset for UART_A0 SWRU543 – January 2019 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 558: Uart1Clken Register
1h = Enable UART_A1 clock during sleep mode RUNCLKEN UART_A1_RUN_CLK_ENABLE 0h = Disable UART_A1 clock during run mode 1h = Enable UART_A1 clock during run mode Power, Reset, and Clock Management SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 559: Uart1Swrst Register
1h = UART_A1 clocks and resets are enabled SWRST UART_A1_SOFT_RESET 0h = Deassert the soft reset for UART_A1 1h = Assert the soft reset for UART_A1 SWRU543 – January 2019 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 560: Gpt0Clkcfg Register
1h = Enable the GPT_A0 clock during sleep RUNCLKEN GPT_A0_RUN_CLK_ENABLE 0h = Disable the GPT_A0 clock during run 1h = Enable the GPT_A0 clock during run Power, Reset, and Clock Management SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 561: Gpt0Swrst Register
1h = GPT_A0 clocks and resets are enabled SWRST GPT_A0_SOFT_RESET 0h = Deassert the soft reset for GPT_A0 1h = Assert the soft reset for GPT_A0 SWRU543 – January 2019 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 562: Gpt1Clken Register
1h = Enable the GPT_A1 clock during sleep RUNCLKEN GPT_A1_RUN_CLK_ENABLE 0h = Disable the GPT_A1 clock during run 1h = Enable the GPT_A1 clock during run Power, Reset, and Clock Management SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 563: Gpt1Swrst Register
1h = GPT_A1 clocks and resets are enabled SWRST GPT_A1_SOFT_RESET 0h = Deassert the soft reset for GPT_A1 1h = Assert the soft reset for GPT_A1 SWRU543 – January 2019 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 564: Gpt2Clken Register
1h = Enable the GPT_A2 clock during sleep RUNCLKEN GPT_A2_RUN_CLK_ENABLE 0h = Disable the GPT_A2 clock during run 1h = Enable the GPT_A2 clock during run Power, Reset, and Clock Management SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 565: Gpt2Swrst Register
1h = GPT_A2 clocks and resets are enabled SWRST GPT_A2_SOFT_RESET 0h = Deassert the soft reset for GPT_A2 1h = Assert the soft reset for GPT_A2 SWRU543 – January 2019 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 566: Gpt3Clken Register
1h = Enable the GPT_A3 clock during sleep RUNCLKEN GPT_A3_RUN_CLK_ENABLE 0h = Disable the GPT_A3 clock during run 1h = Enable the GPT_A3 clock during run Power, Reset, and Clock Management SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 567: Gpt3Swrst Register
1h = GPT_A3 clocks and resets are enabled SWRST GPT_A3_SOFT_RESET 0h = Deassert the soft reset for GPT_A3 1h = Assert the soft reset for GPT_A3 SWRU543 – January 2019 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 568: Mcaspclkcfg0 Register
(Fref/Freq) can be represented as = I.F where I is the integer part of the ratio and F is the fractional part of the ratio. Power, Reset, and Clock Management SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 569: Mcaspclkcfg1 Register
1h = Assert the reset for MCASP Frac-clk div 15-10 RESERVED SPARE MCASP_FRAC_DIV_PERIOD. This bit field is not used in hardware. Can be used as a spare RW register. SWRU543 – January 2019 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 570: I2Clcken Register
C clock during sleep RUNCLKEN I2C_RUN_CLK_ENABLE 0h = Disable the I C clock during run 1h = Enable the I C clock during run Power, Reset, and Clock Management SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 571: I2Cswrst Register
C clocks and resets are enabled SWRST I2C_SOFT_RESET 0h = Deassert the soft reset for Shared-I2C 1h = Assert the soft reset for Shared-I2C SWRU543 – January 2019 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 572: Lpdsreq Register
LPDSREQ R-0h R/W-0h Table 15-45. LPDSREQ Register Field Descriptions Field Type Reset Description 31-1 RESERVED LPDSREQ APPS_LPDS_REQ 1h = Request for LPDS Power, Reset, and Clock Management SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 573: Turboreq Register
TURBOREQ R-0h R/W-0h Table 15-46. TURBOREQ Register Field Descriptions Field Type Reset Description 31-1 RESERVED TURBOREQ APPS_TURBO_REQ 1h = Request for TURBO SWRU543 – January 2019 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 574: Dslpwakecfg Register
EXITDSLPBYTMREN DSLP_WAKE_TIMER_ENABLE 0h = Disable deep-sleep wake timer in APPS RCM 1h = Enable deep-sleep wake timer in APPS RCM for deep-sleep Power, Reset, and Clock Management SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 575: Dslptimrcfg Register
OPP during deep-sleep exit 15-0 TIMRCFG DSLP_WAKE_TIMER_WAKE_CFG Configuration (in slow_clks) which indicates when to request for WAKE during deep-sleep exit SWRU543 – January 2019 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 576: Slpwakeen Register
1h = Enable the sleep wakeup due to NWP request EXITBYTIMR SLP_WAKE_TIMER_ENABLE 0h = Disable the sleep wakeup due to sleep-timer 1h = Enable the sleep wakeup due to sleep-timer Power, Reset, and Clock Management SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 577: Slptmrcfg Register
Table 15-50. SLPTMRCFG Register Field Descriptions Field Type Reset Description 31-0 TMRCFG SLP_WAKE_TIMER_CFG Configuration (number of sysclks-80MHz) for the Sleep wake-up timer. SWRU543 – January 2019 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 578: Wakenwp Register
APPS_TO_NWP_WAKEUP_REQUEST. When 1 => APPS generated a wake request to NWP (When NWP is in any of its low- power modes: SLP/DSLP/LPDS) Power, Reset, and Clock Management SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 579: Rcm_Is Register
1h = Indicates that NWP had caused the wakeup from deep-sleep. EXITSLPBYNWP apps_sleep_wake_from_nwp 1h = Indicates that NWP had caused the wakeup from sleep SWRU543 – January 2019 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 580: Rcm_Ien Register
RESERVED PLLLOCKIRQ 0h = Mask this interrupt 1h = Unmask Interrupt to APPS processor when PLL is locked. Power, Reset, and Clock Management SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 581 16.5 Analog Mux Control Registers ................16.6 Pins Available for Applications ..............16.7 Functional Pin Mux Configurations ................. 16.8 Pin Mapping Recommendations SWRU543 – January 2019 I/O Pads and Pin Multiplexing Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 582: 16.1 Overview
On exit from hibernate mode, RET33 returns to level 0 to allow the device firmware and application software to access the I/O pads. I/O Pads and Pin Multiplexing SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 583: Gpio Pin Electrical Specifications (25°C) (Except Pins 29, 30, 45, 50, 52, 53)
Parameter Name Unit Pullup current, V = 2.4 (V = 3.0 V) µA Pulldown current, V = 0.4 (V = 3.0 V) µA SWRU543 – January 2019 I/O Pads and Pin Multiplexing Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 584: 16.3 Analog And Digital Pin Multiplexing
I/Os corresponding to the desired ADC channel (for example, make them Hi-Z). Thereafter, the respective pass switches (S7 to S10) should be enabled. I/O Pads and Pin Multiplexing SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 585 (1) In the configuration shown, pin 46 is used by ANA2_DCDC and is not available as digital pad. (2) In the configuration shown, pin 52 is used by RTC crystal oscillator and is not available as digital pad. SWRU543 – January 2019 I/O Pads and Pin Multiplexing Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 586: Board Configuration To Use Pins 45 And 52
Digital Signal Square Wave Source (VBAT) (in/out) (out only) (1) Board level configuration required to use pins 45 and 52 for digital signals. I/O Pads and Pin Multiplexing SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 587: Analog Mux Control Registers And Bits
I/O Hi-Z before 1: ADC channel 1 path is Bit [2] enabling analog mux, to prevent enabled damaging the device. SWRU543 – January 2019 I/O Pads and Pin Multiplexing Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 588: Board-Level Behavior
Determined by the I/O cell state, Digital I/O cell is directly connected but (1.8-V absolute max. 1.46-V full scale) like other digital I/Os. Hi-Z. I/O Pads and Pin Multiplexing SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 589: Gpio/Pins Available For Application
GPIO17 VDD_DIG1 VIN_IO1 FLASH_SPI_CLK FLASH_SPI_DOUT FLASH_SPI_DIN FLASH_SPI_CS GPIO22 GPIO28 SOP2 0 (TCXO_EN) 0 (TCXO_EN) 0 (TCXO_EN) 0 (TCXO_EN) WLAN_XTAL_N WLAN_XTAL_P VDD_PLL LDO_IN2 SWRU543 – January 2019 I/O Pads and Pin Multiplexing Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 590 SOP1 SOP0 LDO_IN1 VIN_DCDC_ANA DCDC_ANA_SW VIN_DCDC_PA DCDC_PA_SW_P DCDC_PA_SW_N DCDC_PA_OUT DCDC_DIG_SW VIN_DCDC_DIG DCDC_ANA2_SW_P DCDC_ANA2_SW_N VDD_ANA2 VDD_ANA1 VDD_RAM GPIO0 RTC_XTAL_P RTC_XTAL_N GPIO30 VIN_IO2 GPIO1 I/O Pads and Pin Multiplexing SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 591 PAD) Total available for application 16.7 Functional Pin Mux Configurations Pin mux configurations supported in the CC32xx are listed in Table 16-7. SWRU543 – January 2019 I/O Pads and Pin Multiplexing Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 592: Pin Multiplexing
Hibernate mode: The CC32xx device leaves the digital pins in a Hi-Z state without any internal pulls when the device enters hibernate state. This can cause glitches on output lines, unless held at valid levels by external resistors. I/O Pads and Pin Multiplexing SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 593 Parallel Camera Data Hi-Z (0x4402 E0E0) (CAM_D6) Bit 6 UART1_TX UART1 TX Data SDCARD_CLK SD Card Clock GT_CCP07 Timer Capture Port Hi-Z SWRU543 – January 2019 I/O Pads and Pin Multiplexing Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 594 Hi-Z MUXed GPIO23 General-Purpose I/O with GPIO_PAD_CONFIG_23 Hi-Z Hi-Z UART1_TX UART1 TX Data JTAG (0x4402 E0FC) I2C_SCL I2C Clock Hi-Z (Open Drain) I/O Pads and Pin Multiplexing SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 595 This pin is one of three that must have a passive pullup or pulldown resistor on board to configure the chip hardware power-up mode. Because of this, if this pin is used for digital functions, it must be output only. SWRU543 – January 2019 I/O Pads and Pin Multiplexing Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 596 This pin has dual functions: as a SOP (device operation mode) input pin during boot up, and as the 5-GHz switch control (output) pin on power up. I/O Pads and Pin Multiplexing SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 597 For details on proper use, see the Drive Strength and Reset States for Analog-Digital Multiplexed Pins section of the CC3200 data sheet (CC3200 SimpleLink™ Wi-Fi® and Internet-of- Things Solution, a Single-Chip Wireless MCU). SWRU543 – January 2019 I/O Pads and Pin Multiplexing Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 598 Send O (Active Low) McAXR0 I2S Audio Port Data 0 Hi-Z (RX/TX) Connect 32.768-kHz crystal or Force RTC_XTAL_P RTC_XTAL_P Clock external CMOS level clock I/O Pads and Pin Multiplexing SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 599 Device firmware automatically enables the digital path during ROM boot. (13) To use the digital functions, RTC_XTAL_N must be pulled high to V using a 100-kΩ resistor supply SWRU543 – January 2019 I/O Pads and Pin Multiplexing Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 600 For details on proper use, see the Drive Strength and Reset States for Analog-Digital Multiplexed Pins section of the CC3200 data sheet (CC3200 SimpleLink™ Wi-Fi® and Internet-of- Things Solution, a Single-Chip Wireless MCU). I/O Pads and Pin Multiplexing SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 601 For details on proper use, see the Drive Strength and Reset States for Analog-Digital Multiplexed Pins section of the CC3200 data sheet (CC3200 SimpleLink™ Wi-Fi® and Internet-of- Things Solution, a Single-Chip Wireless MCU). SWRU543 – January 2019 I/O Pads and Pin Multiplexing Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 602 SD Card Data Hi-Z Hi-Z Hi-Z (0x4402 E0C4) McAXR0 I2S Audio Port Data (Rx/Tx) GT_CCP00 Timer Capture Port GND_TAB Thermal pad and electrical ground I/O Pads and Pin Multiplexing SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 603: Pin Groups For Audio Interface (I2S)
Pin Group 2 1 (GPIO_10) 7 (GPIO_16) 2 (GPIO_11) 8 (GPIO_17) DATA 64 (GPIO_09) 6 (GPIO_15) IRQ (future support) 63 (GPIO_8) 63 (GPIO_8) SWRU543 – January 2019 I/O Pads and Pin Multiplexing Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 604: Pad Configuration Registers
These four pins are dedicated for the external SPI serial flash. These cannot be used or shared in any way for other functions. I/O Pads and Pin Multiplexing SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 605: Gpio_Pad_Config_0 To Gpio_Pad_Config_32 Register Description
I/Os are in the reset default state (Hi-Z). The application code must configure the I/Os. The application code must also configure any associated analog muxes for pins that are shared by both digital and analog or PM functions. SWRU543 – January 2019 I/O Pads and Pin Multiplexing Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 606: I/O Pad Data And Control Path Architecture In Cc32Xx
Global Control Lines Hibernate Controller Connect to All Digital IOs 16.8.4 CC32xx Pin-mux Examples Table 16-13 lists recommended pin-out for several application classes. I/O Pads and Pin Multiplexing SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 607: Recommended Pin Multiplexing Configurations
The device supports the feeding of an external 32.768-kHz clock. This configuration frees one pin (32K_XTAL_N) to use in output-only mode with a 100K pullup. SWRU543 – January 2019 I/O Pads and Pin Multiplexing Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 608 GPIO_28 GPIO_28 GPIO_28 GPIO_28 GPIO_28 GPIO_28 GPIO_28 GPIO_28 GPIO_28 GT_PWM2 GT_PWM2 GT_PWM2 GT_PWM2 GT_PWM2 GT_PWM2 GT_PWM2 TCXO_EN GT_PWM2 GT_PWM2 GPIO_25 out only I/O Pads and Pin Multiplexing SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 609: Wake On Pad For Hibernate Mode
FALL EDGE TRIGGER IO CELL MASK BIT LEVEL = 0 TRIGGER LEVEL = 1 TRIGGER RISE EDGE TRIGGER FALL EDGE TRIGGER IO CELL SWRU543 – January 2019 I/O Pads and Pin Multiplexing Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 610: Sense-On-Power Configurations
WLAN analog test pins, and are not available for application. After wakeup, these I/O are also used for controlling the 5G RF switch. I/O Pads and Pin Multiplexing SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 611 ........................... Topic Page ....................17.1 AES Overview ................17.2 AES Functional Description ............... 17.3 AES Module Programming Guide ....................17.4 AES Registers SWRU543 – January 2019 Advance Encryption Standard Accelerator (AES) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 612 The following sections describe the features of the AES module. 17.2.1 AES Block Diagram Figure 17-1 shows the AES block diagram. A single-core/dual-interface architecture is used. Advance Encryption Standard Accelerator (AES) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 613: Aes Block Diagram
AES key scheduler: Generates AES encryption and decryption (round) keys • AES encryption core: The AES encryption algorithm • AES decryption core: The AES decryption algorithm SWRU543 – January 2019 Advance Encryption Standard Accelerator (AES) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 614 Once a decryption key is generated, subsequent decryption operations with the same key use this generated decryption key directly. Advance Encryption Standard Accelerator (AES) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 615: Key-Block-Round Combinations
(offsets). The first row (r = 0) is not shifted. SWRU543 – January 2019 Advance Encryption Standard Accelerator (AES) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 616: Aes - Ecb Feedback Mode
For decryption, the cryptographic core operates in reverse: the decryption data path is used for data processing, whereas encryption uses the encryption data path. Figure 17-2. AES - ECB Feedback Mode Advance Encryption Standard Accelerator (AES) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 617: Aes - Cbc Feedback Mode
The operation is reversed for decryption, resulting in an XOR at the output of the cryptographic core. The input cipher text of the current operation is the IV for the next operation. Figure 17-3. AES - CBC Feedback Mode SWRU543 – January 2019 Advance Encryption Standard Accelerator (AES) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 618: Aes Encryption With Ctr/Icm Mode
Figure 17-4. AES Encryption With CTR/ICM Mode NOTE: The value for n can be 1, 2, 3, or 4 for CTR mode and is ½ for ICM mode. Advance Encryption Standard Accelerator (AES) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 619: Aes - Cfb Feedback Mode
IV register as the next input for the cryptographic core. The decryption operation is reversed, but the cryptographic core still performs encryption. Figure 17-5. AES - CFB Feedback Mode SWRU543 – January 2019 Advance Encryption Standard Accelerator (AES) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 620: Aes - F8 Mode
IV, and a block counter. The output of the cryptographic core is XORed with the input to create the result. In this mode, encryption and decryption use the same operations. Figure 17-6. AES - F8 Mode Advance Encryption Standard Accelerator (AES) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 621: Aes - Xts Operation
Figure 17-7. AES - XTS Operation NOTE: The IV is created with an initial encryption, followed by an LFSR operation for each new block. SWRU543 – January 2019 Advance Encryption Standard Accelerator (AES) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 622: Aes - F9 Operation
IV for the next block. The result is the output of the last XOR operation of the cryptographic core output. Figure 17-8. AES - F9 Operation Advance Encryption Standard Accelerator (AES) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 623: Aes - Cbc-Mac Authentication Mode
The result is the cryptographic core output of the last encryption operation. Figure 17-9. AES - CBC-MAC Authentication Mode SWRU543 – January 2019 Advance Encryption Standard Accelerator (AES) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 624: Aes - Gcm Operation
(intermediate) authentication result. For more information about the GCM protocol, see GCM Protocol Operation in Section 17.2.3.2. Figure 17-10. AES - GCM Operation Advance Encryption Standard Accelerator (AES) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 625: Aes - Ccm Operation
XORed with the intermediate authentication result. The XOR result is used as input for a second encryption operation to calculate the next (intermediate) authentication result. Figure 17-11. AES - CCM Operation SWRU543 – January 2019 Advance Encryption Standard Accelerator (AES) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 626: Interrupts And Events
Event Description AES_IRQSTATUS[3]: CONTEXT_OUT Context output interrupt AES_IRQSTATUS[2]: DATA_OUT Data output interrupt AES_IRQSTATUS[1]: DATA_IN Data input interrupt AES_IRQSTATUS[0]: CONTEXT_IN Context input interrupt Advance Encryption Standard Accelerator (AES) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 627 3. Select the IV counter by programming the CTR_WIDTH field in the AES_CTRL register. 4. Load the AES Initialization Vector Input n (AES_IV_IN_n) registers. SWRU543 – January 2019 Advance Encryption Standard Accelerator (AES) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 628 1. Enable CBC mode by setting the MODE bit in the AES_CTRL register. 2. Load the AES Initialization Vector Input n (AES_IV_IN_n) registers. Advance Encryption Standard Accelerator (AES) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 629: Aes Polling Mode
AES Data RW Plaintext/Ciphertext 0 (AES_DATA_IN_0) registers • AES Control (AES_CTRL) register • AES Hash Tag Out 0 (AES_TAG_OUT_0) register Figure 17-12. AES Polling Mode SWRU543 – January 2019 Advance Encryption Standard Accelerator (AES) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 630 AES interrupt service. The registers used during event servicing follow: • AES_IRQSTATUS • AES_KEY1_n • AES_KEY2_n • AES_IV_IN_n • AES_DATA_IN_n • AES_TAG_OUT_n • AES_IRQENABLE Advance Encryption Standard Accelerator (AES) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 631: Aes Interrupt Service
AES Module Programming Guide www.ti.com Figure 17-13. AES Interrupt Service SWRU543 – January 2019 Advance Encryption Standard Accelerator (AES) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 632: Aes Registers
Section 17.4.39 828h DTHE_AES_MIS AES Interrupt Masked interrupt Status register Section 17.4.40 82Ch DTHE_AES_IC AES Interrupt Clear Interrupt Status register Section 17.4.41 Advance Encryption Standard Accelerator (AES) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 633: Aes_Key2_6 Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 17-5. AES_KEY2_7 Register Field Descriptions Field Type Reset Description 31-0 Key data SWRU543 – January 2019 Advance Encryption Standard Accelerator (AES) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 634: Aes_Key2_4 Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 17-7. AES_KEY2_5 Register Field Descriptions Field Type Reset Description 31-0 Key data Advance Encryption Standard Accelerator (AES) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 635: Aes_Key2_2 Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 17-9. AES_KEY2_3 Register Field Descriptions Field Type Reset Description 31-0 Key data SWRU543 – January 2019 Advance Encryption Standard Accelerator (AES) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 636: Aes_Key2_0 Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 17-11. AES_KEY2_1 Register Field Descriptions Field Type Reset Description 31-0 Key data Advance Encryption Standard Accelerator (AES) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 637: Aes_Key1_6 Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 17-13. AES_KEY1_7 Register Field Descriptions Field Type Reset Description 31-0 Key data SWRU543 – January 2019 Advance Encryption Standard Accelerator (AES) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 638: Aes_Key1_4 Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 17-15. AES_KEY1_5 Register Field Descriptions Field Type Reset Description 31-0 Key data Advance Encryption Standard Accelerator (AES) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 639: Aes_Key1_2 Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 17-17. AES_KEY1_3 Register Field Descriptions Field Type Reset Description 31-0 Key data SWRU543 – January 2019 Advance Encryption Standard Accelerator (AES) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 640: Aes_Key1_0 Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 17-19. AES_KEY1_1 Register Field Descriptions Field Type Reset Description 31-0 Key data Advance Encryption Standard Accelerator (AES) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 641: Aes_Iv_In_0 Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 17-21. AES_IV_IN_1 Register Field Descriptions Field Type Reset Description 31-0 DATA IV data SWRU543 – January 2019 Advance Encryption Standard Accelerator (AES) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 642: Aes_Iv_In_2 Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 17-23. AES_IV_IN_3 Register Field Descriptions Field Type Reset Description 31-0 DATA IV data Advance Encryption Standard Accelerator (AES) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 643: Aes_Ctrl Register
AES-CCM is selected; this is a combined mode, using AES for both authentication and encryption. No additional mode selection is required. 0h = Other mode selected 1h = CCM mode selected SWRU543 – January 2019 Advance Encryption Standard Accelerator (AES) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 644 Key Size 0h = Reserved 1h = Key is 128 bits 2h = Key is 192 bits 3h = Key is 256 Advance Encryption Standard Accelerator (AES) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 645 OUTPUT_READY If 1, this read-only status bit indicates that an AES output block is available for the host to retrieve. SWRU543 – January 2019 Advance Encryption Standard Accelerator (AES) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 646: Aes_C_Length_0 Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 17-25. AES_C_LENGTH_0 Register Field Descriptions Field Type Reset Description 31-0 LENGTH Data length (LSW) Advance Encryption Standard Accelerator (AES) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 647: Aes_C_Length_1 Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 17-26. AES_C_LENGTH_1 Register Field Descriptions Field Type Reset Description 31-29 RESERVED 28-0 LENGTH Data length (MSW) SWRU543 – January 2019 Advance Encryption Standard Accelerator (AES) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 648: Aes_Auth_Length Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 17-27. AES_AUTH_LENGTH Register Field Descriptions Field Type Reset Description 31-0 AUTH Data Advance Encryption Standard Accelerator (AES) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 649: Aes_Data_In_0 Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 17-29. AES_DATA_IN_1 Register Field Descriptions Field Type Reset Description 31-0 DATA Data to encrypt or decrypt SWRU543 – January 2019 Advance Encryption Standard Accelerator (AES) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 650: Aes_Data_In_2 Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 17-31. AES_DATA_IN_3 Register Field Descriptions Field Type Reset Description 31-0 DATA Data to encrypt or decrypt Advance Encryption Standard Accelerator (AES) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 651: Aes_Tag_Out_0 Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 17-33. AES_TAG_OUT_1 Register Field Descriptions Field Type Reset Description 31-0 HASH Hash result (MSW) SWRU543 – January 2019 Advance Encryption Standard Accelerator (AES) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 652: Aes_Tag_Out_2 Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 17-35. AES_TAG_OUT_3 Register Field Descriptions Field Type Reset Description 31-0 HASH Hash result (LSW) Advance Encryption Standard Accelerator (AES) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 653: Aes_Revision Register
Indicates a special version for a particular device. Consequence of use may avoid use of standard Chip Support Library (CSL) / Drivers. 0h = (Read): Non-custom (standard) revision SWRU543 – January 2019 Advance Encryption Standard Accelerator (AES) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 654: Aes_Revision Register Field Descriptions
IP bugs. An RTL release (say for silicon PG1.1) that occurs due to bug fix should document the corresponding spec number (X.Y.S) in its release notes. Advance Encryption Standard Accelerator (AES) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 655: Aes_Sysconfig Register
1h = DMA enabled DMA_REQ_DATA_IN_EN R/W If set to 1, the DMA input request is enabled. 0h = DMA disabled 1h = DMA enabled RESERVED SWRU543 – January 2019 Advance Encryption Standard Accelerator (AES) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 656: Aes_Irqstatus Register
This bit indicates data input interrupt is active, and triggers the interrupt output CONTEXT_IN This bit indicates context interrupt is active, and triggers the interrupt output. Advance Encryption Standard Accelerator (AES) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 657: Aes_Irqenable Register
This bit indicates data input interrupt is active, and triggers the interrupt output CONTEXT_IN This bit indicates context interrupt is active, and triggers the interrupt output. SWRU543 – January 2019 Advance Encryption Standard Accelerator (AES) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 658: Cryptoclken Register
Reset Description 31-1 RESERVED RUNCLKEN CRYPTO_RUN_CLK_ENABLE: 0h = Enable the crypto clock during run 1h = Disable the crypto clock during run Advance Encryption Standard Accelerator (AES) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 659: Dthe_Aes_Im Register
Context out: This interrupt is raised when DMA completes the output context movement from internal register. Context in: This interrupt is raised when DMA completes context write to internal register. SWRU543 – January 2019 Advance Encryption Standard Accelerator (AES) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 660: Dthe_Aes_Ris Register
31-4 RESERVED Dout Output data movement is done Input data movement is done Cout Context output is done Context input is done Advance Encryption Standard Accelerator (AES) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 661: Dthe_Aes_Mis Register
31-4 RESERVED Dout Output data movement is done Input data movement is done Cout Context output is done Context input is done SWRU543 – January 2019 Advance Encryption Standard Accelerator (AES) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 662: Dthe_Aes_Ic Register
Clear “output data movement done” flag Clear “input data movement done” flag Cout Clear “context output done” flag Clear “context input done” flag Advance Encryption Standard Accelerator (AES) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 663 DES Block Diagram ..............18.3 DES-Supported Modes of Operation ..... 18.4 DES Module Programming Guide – Low-Level Programming Models ....................18.5 DES Registers SWRU543 – January 2019 Data Encryption Standard Accelerator (DES) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 664: Key Repartition
Packets (64-bit blocks) must be parsed into blocks and sequentially fed into the DES, which can buffer the block being processed, as well as an additional block that may be queued in advance. Data Encryption Standard Accelerator (DES) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 665: Des Block Diagram
Interrupt Enable (DES_IRQENABLE) register. The following events can generate an interrupt bit to be set in the DES_IRQSTATUS register: • New context input required • Data input required • Data output ready SWRU543 – January 2019 Data Encryption Standard Accelerator (DES) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 666 For decryption, the DES core operates in reverse, meaning the decrypt key sequence is used for the data processing, where encryption uses the encrypt key sequence. Data Encryption Standard Accelerator (DES) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 667: Des - Ecb Feedback Mode
IV; the result is XORed with the data. The result is fed back through the IV register, as the next input for the crypto core. The decrypt operation is reversed, but the crypto core still performs an encryption. SWRU543 – January 2019 Data Encryption Standard Accelerator (DES) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 668: Des3Des - Cfb Feedback Mode
Register/Bit Field/Programming Model Value Load key 1 LSW. DES_KEY1_L[31:0] KEY1_L – Load key 1 MSW. DES_KEY1_H[31:0] KEY1_H – Select DES algorithm. DES_CTRL[3] TDES Data Encryption Standard Accelerator (DES) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 669: 3Des Algorithm Type Configuration
18.4.2.1 Main Sequence – DES Polling Mode Figure 18-5 shows DES polling mode. The registers used in DES polling mode are: DES_DATA_L, DES_DATA_H, and DES_CTRL. SWRU543 – January 2019 Data Encryption Standard Accelerator (DES) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 670: Des Polling Mode
DES Module Programming Guide – Low-Level Programming Models www.ti.com Figure 18-5. DES Polling Mode Data Encryption Standard Accelerator (DES) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 671: Des Interrupt Service
Figure 18-6 shows the DES interrupt service. The registers used during event servicing are: DES_IRQSTATUS, DES_DATA_L, and DES_DATA_H. Figure 18-6. DES Interrupt Service SWRU543 – January 2019 Data Encryption Standard Accelerator (DES) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 672: Des Context Input Event Service
DES_KEY2_L, DES_KEY2_H, DES_KEY3_L, DES_KEY3_H, DES_IV_L, DES_IV_H, and DES_LENGTH. Should DES_SYSCONFIG be shown in Figure 18-7? Figure 18-7. DES Context Input Event Service Data Encryption Standard Accelerator (DES) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 673: Des Register Map
Section 18.5.16 1034h DES_SYSCONFIG DES System Configuration Section 18.5.17 103Ch DES_IRQSTATUS DES Interrupt Status Section 18.5.18 1040h DES_IRQENABLE DES Interrupt Enable Section 18.5.19 SWRU543 – January 2019 Data Encryption Standard Accelerator (DES) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 674: Dthe_Des_Im Register
FIFO of the engine. RESERVED Context in: this interrupt is raised when the DMA completes context write to the internal register. Data Encryption Standard Accelerator (DES) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 675: Dthe_Des_Ris Register
Field Type Reset Description 31-4 RESERVED Dout Output Data movement is done. Input Data movement is done. RESERVED Context input is done. SWRU543 – January 2019 Data Encryption Standard Accelerator (DES) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 676: Dthe_Des_Mis Register
Field Type Reset Description 31-4 RESERVED Dout Output Data movement is done. Input Data movement is done. RESERVED Context input is done. Data Encryption Standard Accelerator (DES) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 677: Dthe_Des_Ic Register
Description 31-4 RESERVED Dout Clear “output data movement done” flag. Clear “input data movement done” flag. RESERVED Clear “context input done” flag. SWRU543 – January 2019 Data Encryption Standard Accelerator (DES) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 678: Des_Key3_L Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 18-12. DES_KEY3_L Register Field Descriptions Field Type Reset Description 31-0 KEY3_L Data for key3 Data Encryption Standard Accelerator (DES) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 679: Des_Key3_H Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 18-13. DES_KEY3_H Register Field Descriptions Field Type Reset Description 31-0 KEY3_H Data for key3 SWRU543 – January 2019 Data Encryption Standard Accelerator (DES) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 680: Des_Key2_L Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 18-14. DES_KEY2_L Register Field Descriptions Field Type Reset Description 31-0 KEY2_L Data for key2 Data Encryption Standard Accelerator (DES) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 681: Des_Key2_H Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 18-15. DES_KEY2_H Register Field Descriptions Field Type Reset Description 31-0 KEY2_H Data for key2 SWRU543 – January 2019 Data Encryption Standard Accelerator (DES) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 682: Des_Key1_L Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 18-16. DES_KEY1_L Register Field Descriptions Field Type Reset Description 31-0 KEY1_L Data for key1 Data Encryption Standard Accelerator (DES) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 683: Des_Key1_H Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 18-17. DES_KEY1_H Register Field Descriptions Field Type Reset Description 31-0 KEY1_H Data for key1 SWRU543 – January 2019 Data Encryption Standard Accelerator (DES) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 684: Des_Iv_L Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 18-18. DES_IV_L Register Field Descriptions Field Type Reset Description 31-0 IV_L Initialization vector for CBC, CFB modes. Data Encryption Standard Accelerator (DES) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 685: Des_Iv_H Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 18-19. DES_IV_H Register Field Descriptions Field Type Reset Description 31-0 IV_H Initialization vector for CBC, CFB modes. SWRU543 – January 2019 Data Encryption Standard Accelerator (DES) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 686: Des_Ctrl Register
1h = Encryption is selected INPUT_READY When 1, ready to encrypt or decrypt data. OUTPUT_READY When 1, data decrypted or encrypted ready. Data Encryption Standard Accelerator (DES) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 687: Des_Length Register
– 1) bytes are allowed. A write to this register triggers the engine to start using this context. For a host read operation, these registers return all zeroes. SWRU543 – January 2019 Data Encryption Standard Accelerator (DES) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 688: Des_Data_L Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 18-22. DES_DATA_L Register Field Descriptions Field Type Reset Description 31-0 DATA_L Data for encryption or decryption Data Encryption Standard Accelerator (DES) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 689: Des_Data_H Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 18-23. DES_DATA_H Register Field Descriptions Field Type Reset Description 31-0 DATA_H Data for encryption or decryption SWRU543 – January 2019 Data Encryption Standard Accelerator (DES) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 690: Des_Sysconfig Register
1h = DMA enabled DMA_REQ_DATA_IN_EN R/W If set to 1, the DMA input request is enabled. 0h = DMA disabled 1h = DMA enabled RESERVED Data Encryption Standard Accelerator (DES) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 691: Des_Irqstatus Register
This bit indicates data input interrupt is active and triggers the interrupt output. CONTEX_IN This bit indicates context interrupt is active and triggers the interrupt output. SWRU543 – January 2019 Data Encryption Standard Accelerator (DES) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 692: Des_Irqenable Register
If this bit is set to 1, the data input interrupt is enabled. M_CONTEX_IN If this bit is set to 1, the context interrupt is enabled. Data Encryption Standard Accelerator (DES) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 693 Supports µDMA operation for data and context in and result out transfers • Supports interrupt to read the digest (signature) ........................... Topic Page ................ 19.1 SHA/MD5 Functional Description ..................19.2 SHA-MD5 Registers SWRU543 – January 2019 SHA/MD5 Accelerator Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 694: Sha/Md5 Module Block Diagram
A loaded data block must always be a full 64 bytes (512 bits) long. SHA/MD5 Accelerator SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 695: Interrupts And Events
The SHA/MD5 module can run the SHA-1, SHA-224, SHA-256, and MD5 algorithms, depending on the value of the ALGO bit field in the SHA Mode (SHAMD5_MODE) register. See Table 19-2. SWRU543 – January 2019 SHA/MD5 Accelerator Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 696: Sha/Md5 Module Algorithm Selection
The processor can then read the eight digest registers A to H that contain the hash or HMAC result. If the hash is an intermediate result of a larger hash, the digest count register must also be read and saved. See Table 19-3 Table 19-4. SHA/MD5 Accelerator SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 697: Outer Digest Registers
Inner digest Inner digest HMAC key [31:0] [63:32] [479:448] SHAMD5_IDIGEST_H 0x03C Inner digest HMAC key [31:0] [511:480] NOTE: Inner digests are initial, intermediate, and result digests. SWRU543 – January 2019 SHA/MD5 Accelerator Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 698 When HMAC_KEY_PROC is 1, these registers must be written with the upper 256 bits of the HMAC key to be processed in little-endian format (first byte of key string in bits [7:0]). SHA/MD5 Accelerator SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 699: Sha Digest Processed In Three Passes
Round 2 digest WRITE: 128 Write: Last byte of message calculation LENGTH=1 ALGO (dependent on the algorithm to apply) ALGO_CONSTANT=0 CLOSE_HASH=1 Final digest READ: 129 SWRU543 – January 2019 SHA/MD5 Accelerator Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 700: Sha Digest Processed In One Pass
SHAMD5_IRQSTATUS register then indicates that the hash operation is complete. If the PIT_EN bit in the SHAMD5_SYSCONFIG register is set, an interrupt (active low) is also generated to indicate the hash completion. SHA/MD5 Accelerator SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 701 1. Load the key value in the SHAMD5_ODIGEST_A/SHAMD5_IDIGEST_A to SHAMD5_ODIGEST_H/SHAMD5_IDIGEST_H registers. 2. Pad the rest of the SHA _ODIGEST_x and SHAMD5_IDIGEST registers with zeros. 3. Load the message in the SHAMD5_DATA_n_IN FIFO registers. SWRU543 – January 2019 SHA/MD5 Accelerator Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 702: Continuing A Prior Hmac
Select the SHA-1 hash function. SHAMD5_MODE[2:1] ALGO Select a new hash operation. SHAMD5_MODE[3] ALGO_CONSTANT Close the hash; the key is processed in single pass. SHAMD5_MODE[4] CLOSE_HASH SHA/MD5 Accelerator SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 703: Sha/Md5 Polling Mode
Enable the DMA request to the CDMA controller. SHAMD5_SYSCONFIG[3] P DMA_EN Load the message length; this is the trigger to start SHAMD5_LENGTH[31:0] LENGTH – processing. SWRU543 – January 2019 SHA/MD5 Accelerator Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 704: Sha/Md5 Interrupt Subroutine
The following registers are used in the SHA/MD5 interrupt routine: SHAMD5_IRQSTATUS, SHAMD5_DATA_n_IN, SHAMD5_ODIGEST_A, SHAMD5_DIGEST_COUNT, SHAMD5_LENGTH, and SHAMD5_IDIGEST_A. Figure 19-3. SHA/MD5 Interrupt Subroutine SHA/MD5 Accelerator SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 705: Sha-Md5 Registers
DTHE_SHA_IM SHA Interrupt Mask Set Section 19.2.39 814h DTHE_SHA_RIS SHA Interrupt Raw Interrupt Status Section 19.2.40 818h DTHE_SHA_MIS SHA Interrupt Masked interrupt Status Section 19.2.41 SWRU543 – January 2019 SHA/MD5 Accelerator Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 706: Overview Of Public World, Inner And Outer Digest Registers, And Usage For Md5, Sha-1, And Sha
Inner Digest* HMAC Key 0x1038 [31:0] [63:32] [479:448 P_HASH_IDIGEST_H Inner Digest* HMAC Key 0x103C [31:0] [511:480] * Note: Inner Digest (initial, intermediate and result digest) SHA/MD5 Accelerator SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 707 HMAC key processing) for subsequent data blocks without having to reload it. This is done by setting HMAC key processing to 0 and Reuse HMAC key to 1 in the SHAMD5_MODE register. SWRU543 – January 2019 SHA/MD5 Accelerator Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 708: Shamd5_Odigest_A Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 19-12. SHAMD5_ODIGEST_A Register Field Descriptions Field Type Reset Description 31-0 DATA Data SHA/MD5 Accelerator SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 709: Shamd5_Odigest_B Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 19-13. SHAMD5_ODIGEST_B Register Field Descriptions Field Type Reset Description 31-0 DATA Data SWRU543 – January 2019 SHA/MD5 Accelerator Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 710: Shamd5_Odigest_C Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 19-14. SHAMD5_ODIGEST_C Register Field Descriptions Field Type Reset Description 31-0 DATA Data SHA/MD5 Accelerator SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 711: Shamd5_Odigest_D Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 19-15. SHAMD5_ODIGEST_D Register Field Descriptions Field Type Reset Description 31-0 DATA Data SWRU543 – January 2019 SHA/MD5 Accelerator Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 712: Shamd5_Odigest_E Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 19-16. SHAMD5_ODIGEST_E Register Field Descriptions Field Type Reset Description 31-0 DATA Data SHA/MD5 Accelerator SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 713: Shamd5_Odigest_F Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 19-17. SHAMD5_ODIGEST_F Register Field Descriptions Field Type Reset Description 31-0 DATA Data SWRU543 – January 2019 SHA/MD5 Accelerator Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 714: Shamd5_Odigest_G Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 19-18. SHAMD5_ODIGEST_G Register Field Descriptions Field Type Reset Description 31-0 DATA Data SHA/MD5 Accelerator SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 715: Shamd5_Odigest_H Register
HMAC key processing) for subsequent data blocks without having to reload it. This is done by setting HMAC key processing to 0 and Reuse HMAC key to 1 in the SHAMD5_MODE register. SWRU543 – January 2019 SHA/MD5 Accelerator Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 716: Shamd5_Idigest_A Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 19-20. SHAMD5_IDIGEST_A Register Field Descriptions Field Type Reset Description 31-0 DATA Data SHA/MD5 Accelerator SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 717: Shamd5_Idigest_B Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 19-21. SHAMD5_IDIGEST_B Register Field Descriptions Field Type Reset Description 31-0 DATA Data SWRU543 – January 2019 SHA/MD5 Accelerator Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 718: Shamd5_Idigest_C Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 19-22. SHAMD5_IDIGEST_C Register Field Descriptions Field Type Reset Description 31-0 DATA Data SHA/MD5 Accelerator SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 719: Shamd5_Idigest_D Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 19-23. SHAMD5_IDIGEST_D Register Field Descriptions Field Type Reset Description 31-0 DATA Data SWRU543 – January 2019 SHA/MD5 Accelerator Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 720: Shamd5_Idigest_E Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 19-24. SHAMD5_IDIGEST_E Register Field Descriptions Field Type Reset Description 31-0 DATA Data SHA/MD5 Accelerator SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 721: Shamd5_Idigest_F Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 19-25. SHAMD5_IDIGEST_F Register Field Descriptions Field Type Reset Description 31-0 DATA Data SWRU543 – January 2019 SHA/MD5 Accelerator Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 722: Shamd5_Idigest_G Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 19-26. SHAMD5_IDIGEST_G Register Field Descriptions Field Type Reset Description 31-0 DATA Data SHA/MD5 Accelerator SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 723: Shamd5_Idigest_H Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 19-27. SHAMD5_IDIGEST_H Register Field Descriptions Field Type Reset Description 31-0 DATA Data SWRU543 – January 2019 SHA/MD5 Accelerator Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 724: Shamd5_Digest_Count Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 19-28. SHAMD5_DIGEST_COUNT Register Field Descriptions Field Type Reset Description 31-0 DATA Data SHA/MD5 Accelerator SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 725: Shamd5_Mode Register
64 bytes to ensure correct operation. Auto-cleared internally when hash closed. 0h = No padding, hash computation can be continued. 1h = Last packet is padded. SWRU543 – January 2019 SHA/MD5 Accelerator Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 726: Shamd5_Mode Register Field Descriptions
These bits select the hash algorithm to be used for processing. 0h = md5_128 algorithm 1h = sha1_160 algorithm 2h = sha2_224 algorithm 3h = sha2_256 algorithm RESERVED SHA/MD5 Accelerator SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 727: Shamd5_Length Register
Also, do not exceed the FIFO size: check the status signals after writing a full block of 16 words or 32 words for SHA-384 and SHA-512. SWRU543 – January 2019 SHA/MD5 Accelerator Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 728 FIFO. A read from these registers (on any address in the address range) returns zeros. SHA/MD5 Accelerator SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 729: Shamd5_Data0_In Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 19-31. SHAMD5_DATA0_IN Register Field Descriptions Field Type Reset Description 31-0 DATA0_IN Data SWRU543 – January 2019 SHA/MD5 Accelerator Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 730: Shamd5_Data1_In Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 19-32. SHAMD5_DATA1_IN Register Field Descriptions Field Type Reset Description 31-0 DATA1_IN Data SHA/MD5 Accelerator SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 731: Shamd5_Data2_In Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 19-33. SHAMD5_DATA2_IN Register Field Descriptions Field Type Reset Description 31-0 DATA2_IN Data SWRU543 – January 2019 SHA/MD5 Accelerator Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 732: Shamd5_Data3_In Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 19-34. SHAMD5_DATA3_IN Register Field Descriptions Field Type Reset Description 31-0 DATA3_IN Data SHA/MD5 Accelerator SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 733: Shamd5_Data4_In Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 19-35. SHAMD5_DATA4_IN Register Field Descriptions Field Type Reset Description 31-0 DATA4_IN Data SWRU543 – January 2019 SHA/MD5 Accelerator Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 734: Shamd5_Data5_In Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 19-36. SHAMD5_DATA5_IN Register Field Descriptions Field Type Reset Description 31-0 DATA5_IN Data SHA/MD5 Accelerator SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 735: Shamd5_Data6_In Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 19-37. SHAMD5_DATA6_IN Register Field Descriptions Field Type Reset Description 31-0 DATA6_IN Data SWRU543 – January 2019 SHA/MD5 Accelerator Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 736: Shamd5_Data7_In Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 19-38. SHAMD5_DATA7_IN Register Field Descriptions Field Type Reset Description 31-0 DATA7_IN Data SHA/MD5 Accelerator SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 737: Shamd5_Data8_In Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 19-39. SHAMD5_DATA8_IN Register Field Descriptions Field Type Reset Description 31-0 DATA8_IN Data SWRU543 – January 2019 SHA/MD5 Accelerator Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 738: Shamd5_Data9_In Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 19-40. SHAMD5_DATA9_IN Register Field Descriptions Field Type Reset Description 31-0 DATA9_IN Data SHA/MD5 Accelerator SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 739: Shamd5_Data10_In Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 19-41. SHAMD5_DATA10_IN Register Field Descriptions Field Type Reset Description 31-0 DATA10_IN Data SWRU543 – January 2019 SHA/MD5 Accelerator Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 740: Shamd5_Data11_In Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 19-42. SHAMD5_DATA11_IN Register Field Descriptions Field Type Reset Description 31-0 DATA11_IN Data SHA/MD5 Accelerator SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 741: Shamd5_Data12_In Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 19-43. SHAMD5_DATA12_IN Register Field Descriptions Field Type Reset Description 31-0 DATA12_IN Data SWRU543 – January 2019 SHA/MD5 Accelerator Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 742: Shamd5_Data13_In Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 19-44. SHAMD5_DATA13_IN Register Field Descriptions Field Type Reset Description 31-0 DATA13_IN Data SHA/MD5 Accelerator SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 743: Shamd5_Data14_In Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 19-45. SHAMD5_DATA14_IN Register Field Descriptions Field Type Reset Description 31-0 DATA14_IN Data SWRU543 – January 2019 SHA/MD5 Accelerator Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 744: Shamd5_Data15_In Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 19-46. SHAMD5_DATA15_IN Register Field Descriptions Field Type Reset Description 31-0 DATA15_IN Data SHA/MD5 Accelerator SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 745: Shamd5_Sysconfig Register
RESERVED PDMA_EN Enable DMA 0h = DMA disabled 1h = DMA enabled PIT_EN Enable Interrupt 0h = Interrupt disabled 1h = Interrupt enabled RESERVED SWRU543 – January 2019 SHA/MD5 Accelerator Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 746: Shamd5_Irqstatus Register
Indicates that the secure-side data FIFO is ready to receive the next 64-byte data block. OUTPUT_READY Indicates that a (partial) result or saved context is available from the secure-side context output registers. SHA/MD5 Accelerator SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 747: Shamd5_Irqenable Register
Table 19-49. SHAMD5_IRQENABLE Register Field Descriptions Field Type Reset Description 31-4 RESERVED M_CONTEXT_READY Mask for context ready M_PARTHASH_READY Mask for partial hash M_INPUT_READY Mask for input_ready M_OUTPUT_READY Mask for output_ready SWRU543 – January 2019 SHA/MD5 Accelerator Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 748: Dthe_Sha_Im Register
Context out: this interrupt is raised when DMA completes the output context movement from internal register. Context in: this interrupt is raised when DMA completes a context write to internal register SHA/MD5 Accelerator SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 749: Dthe_Sha_Ris Register
Table 19-51. DTHE_SHA_RIS Register Field Descriptions Field Type Reset Description 31-3 RESERVED Input data movement is done Cout Context output is done Context input is done SWRU543 – January 2019 SHA/MD5 Accelerator Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 750: Dthe_Sha_Mis Register
Table 19-52. DTHE_SHA_MIS Register Field Descriptions Field Type Reset Description 31-3 RESERVED Input data movement is done Cout Context output is done Context input is done SHA/MD5 Accelerator SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 751: Dthe_Sha_Ic Register
Table 19-53. DTHE_SHA_IC Register Field Descriptions Field Type Reset Description 31-3 RESERVED R/WC Clear “input data movement done” flag Cout Clear “output done” flag Clear “input done” flag SWRU543 – January 2019 SHA/MD5 Accelerator Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 752 Supports MSB AND LSB • Supports CCITT post-processing ........................... Topic Page ..................20.1 Functional Description ................20.2 Initialization and Configuration ....................20.3 CRC Registers Cyclical Redundancy Check (CRC) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 753 0x12, 0x34, 0x56, and 0x78 are copied into memory in that order and the word is stored as 0x78563412, where 0x12 is written as byte 0, 0x34 is written as byte 1, and so forth. SWRU543 – January 2019 Cyclical Redundancy Check (CRC) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 754: Endian Configuration
Halfwords are swapped but bytes are not B1[8:15],B0[0:7],B3[24:31],B2[16:23] swapped in halfword. {B1[15:8], B0[7:0], B3[31:24], B2[23:16]} Bytes are swapped in halfwords and halfwords B0[0:7],B1[8:15],B2[16:23],B3[24:31] are swapped. {B0[7:0], B1[15:8], B2[23:16], B3[31:24]} Cyclical Redundancy Check (CRC) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 755 If operating in word mode, the CRCDIN register should be written in the following order: 1. {D3, D2, D1, D0} 2. {D7, D6, D5, D4} 3. {D11, D10, D9, D8} 4..5..SWRU543 – January 2019 Cyclical Redundancy Check (CRC) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 756: Crc Registers
Section 20.3.1 C10h CRCSEED CRC SEED/Context Section 20.3.2 C14h CRCDIN CRC Data Input Section 20.3.3 C18h CRCRSLTPP CRC Post Processing Result Section 20.3.4 Cyclical Redundancy Check (CRC) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 757: Crcctrl Register
0h = No change to result. 1h = Bit reverse the input byte for all bytes in a word. RESERVED SWRU543 – January 2019 Cyclical Redundancy Check (CRC) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 758 1h = Polynomial 0x1021 2h = Polynomial 0x4C11DB7 3h = Polynomial 0x1EDC6F41 4h - 7h = Reserved 8h = TCP checksum 9h - Fh = Reserved Cyclical Redundancy Check (CRC) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 759: Crcseed Register
This register contains the starting seed of the CRC and checksum operation. This register also holds the latest result of CRC or checksum operation. SWRU543 – January 2019 Cyclical Redundancy Check (CRC) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 760: Crcdin Register
Table 20-6. CRCDIN Register Field Descriptions Field Type Reset Description 31-0 DATAIN Data Input This register contains the input data value for the CRC or checksum operation. Cyclical Redundancy Check (CRC) SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 761: Crcrsltpp Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 20-7. CRCRSLTPP Register Field Descriptions Field Type Reset Description 31-0 RSLTPP Post Processing Result This register contains the post-processed CRC result. SWRU543 – January 2019 Cyclical Redundancy Check (CRC) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 762 21.8 Programming, Bootstrapping, and Updating the Flash User Application ............21.9 Image Authentication and Integrity Check ..........21.10 Debugging Flash User Application Using JTAG On-Chip Parallel Flash SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 763 2. Write the flash memory write key and the ERASE bit (a value of 0xA442.0002) to the FMC register. 3. Poll the FMC register until the ERASE bit is cleared. SWRU543 – January 2019 On-Chip Parallel Flash Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 764 3. Write the flash memory write key and the WRBUF bit to the FMC2 register. 4. Poll the FMC register until the WRITE bit is cleared. On-Chip Parallel Flash SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 765: Flash Registers
Section 21.5.6 FMC2 Flash Memory Control 2 Section 21.5.7 FWBVAL Flash Write Buffer Valid Section 21.5.8 100h–17Ch FWBn Flash Write Buffer n Section 21.5.9 SWRU543 – January 2019 On-Chip Parallel Flash Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 766: Fma Register
19-0 OFFSET Address Offset Address offset in flash memory where the operation is performed, except for nonvolatile registers On-Chip Parallel Flash SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 767: Fmd Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 21-3. FMD Register Field Descriptions Field Type Reset Description 31-0 DATA Data Value Data value for write operation SWRU543 – January 2019 On-Chip Parallel Flash Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 768: Fmc Register
1h = Set this bit to erase the flash memory page specified by the contents of the FMA register. When read, 1 indicates that the previous page-erase access is not complete. On-Chip Parallel Flash SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 769 1h = Set this bit to write the data stored in the FMD register into the flash memory location specified by the contents of the FMA register. When read, 1 indicates that the write update access is not complete. SWRU543 – January 2019 On-Chip Parallel Flash Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 770: Fcris Register
Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. On-Chip Parallel Flash SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 771 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SWRU543 – January 2019 On-Chip Parallel Flash Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 772: Fcim Register
Software should not rely on the value of a reserved bit. To provide RESERVED compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. On-Chip Parallel Flash SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 773: Fcmisc Register
Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SWRU543 – January 2019 On-Chip Parallel Flash Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 774 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. On-Chip Parallel Flash SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 775: Fmc2 Register
1h = Set this bit to write the data stored in the FWBn registers to the location specified by the contents of the FMA register. SWRU543 – January 2019 On-Chip Parallel Flash Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 776: Fwbval Register
1h = The corresponding FWBn register has been updated since the last buffer write operation and is ready to be written to flash memory. On-Chip Parallel Flash SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 777: Fwbn Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 21-10. FWBn Register Field Descriptions Field Type Reset Description 31-0 DATA Data to be written into the flash memory SWRU543 – January 2019 On-Chip Parallel Flash Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 778: Cc3235Sf Boot Flow
The debug image is handled as a special case, where the serial flash must be formatted in development mode. In development mode, unlike production mode, the JTAG access is granted to external debuggers. On-Chip Parallel Flash SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 779: Flash Memory Partition
Image Size Header Valid Marker 0x0100_0000 NOTE: The effective maximum size of the user application is limited to 1022KB, and linked to run from 0x0100_0800. SWRU543 – January 2019 On-Chip Parallel Flash Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 780: User Application Image Binary Structure On Serial Flash
User Application Image linked to address 0x0100_0800 Reset Vector (PC) Initial Stack Pointer (SP) Auto appended by Image SHA pattern 20 Bytes ImageCreator tool On-Chip Parallel Flash SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 781 Figure 21-13 shows a simplified view of the image transfer process, from serial flash to on-chip flash in a CC3235SF device. SWRU543 – January 2019 On-Chip Parallel Flash Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 782: On-Chip Flash Programming And Update
SHA-1 hash of the on serial flash in a file "/sys/mcuflashimghash.bin" 32 bit Image Size 32 bit Header Valid SHA-1 Hash Pattern Serial Flash On-Chip Flash On-Chip Parallel Flash SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 783: Flash Debug Image Layout
Figure 21-14. Flash Debug Image Layout 0x0110_0000 1022 KB User Application Image 0x0100_0800 Reserved 2 KB 0xEFA3247D header Image Size 0x5AA5A55A 0x0100_0000 SWRU543 – January 2019 On-Chip Parallel Flash Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 784: Peripheral Samples
SD Host Chapter 11 SDHost FatFS Application Chapter 12 Wi-Fi Audio Application Chapter 13 ADC Reference Parallel Camera Interface Chapter 14 Camera Application Software Development Kit Examples SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 785: Cc3235X Device Miscellaneous Register Summary
Section B.4 0x4402 60A0 DMA_MIS DMA_MIS Register Section B.5 0x4402 60A4 DMA_RIS DMA_RIS Register Section B.6 0x4402 60B0 GPTTRIGSEL GPTTRIGSEL Register Section B.7 SWRU543 – January 2019 CC3235x Device Miscellaneous Registers Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 786: Dma_Imr Register
1h = disable corresponding interrupt APSPIRD APPS_SPI_RD_DMA_DONE_INT_MASK 0h = interrupt enabled 1h = disable corresponding interrupt SDIOMWR SDIOM_WR_DMA_DONE_INT_MASK 0h = interrupt enabled 1h = disable corresponding interrupt CC3235x Device Miscellaneous Registers SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 787 Table B-2. DMA_IMR Register Field Descriptions (continued) Field Type Reset Description SDIOMRD SDIOM_RD_DMA_DONE_INT_MASK 0h = interrupt enabled 1h = disable corresponding interrupt SWRU543 – January 2019 CC3235x Device Miscellaneous Registers Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 788: Dma_Ims Register
1h = Set mask of the corresponding DMA DONE IRQ SDIOMWR SDIOM_WR_DMA_DONE_INT_MASK_SET 0h = No effect 1h = Set mask of the corresponding DMA DONE IRQ CC3235x Device Miscellaneous Registers SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 789 Table B-3. DMA_IMS Register Field Descriptions (continued) Field Type Reset Description SDIOMRD SDIOM_RD_DMA_DONE_INT_MASK_SET 0h = No effect 1h = Set mask of the corresponding DMA DONE IRQ SWRU543 – January 2019 CC3235x Device Miscellaneous Registers Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 790: Dma_Imc Register
1h = Clear mask of the corresponding DMA DONE IRQ SDIOMWR SDIOM_WR_DMA_DONE_INT_MASK_CLR 0h = No effect 1h = Clear mask of the corresponding DMA DONE IRQ CC3235x Device Miscellaneous Registers SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 791 Table B-4. DMA_IMC Register Field Descriptions (continued) Field Type Reset Description SDIOMRD SDIOM_RD_DMA_DONE_INT_MASK_CLR 0h = No effect 1h = Clear mask of the corresponding DMA DONE IRQ SWRU543 – January 2019 CC3235x Device Miscellaneous Registers Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 792: Dma_Icr Register
1h = Clear corresponding interrupt APSPIRD APPS_SPI_RD_DMA_DONE_INT_ACK 0h = No effect 1h = Clear corresponding interrupt SDIOMWR SDIOM_WR_DMA_DONE_INT_ACK 0h = No effect 1h = Clear corresponding interrupt CC3235x Device Miscellaneous Registers SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 793 Table B-5. DMA_ICR Register Field Descriptions (continued) Field Type Reset Description SDIOMRD SDIOM_RD_DMA_DONE_INT_ACK 0h = No effect 1h = Clear corresponding interrupt SWRU543 – January 2019 CC3235x Device Miscellaneous Registers Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 794 0h = Corresponding interrupt is inactive or masked by DMA_DONE_INT mask. 1h = Corresponding interrupt is active and not masked. Read is non- destructive. RESERVED CC3235x Device Miscellaneous Registers SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 795 0h = Corresponding interrupt is inactive or masked by DMA_DONE_INT mask. 1h = Corresponding interrupt is active and not masked. Read is non- destructive. SWRU543 – January 2019 CC3235x Device Miscellaneous Registers Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 796 1h = Corresponding interrupt is active. Read is non-destructive. SDIOMWR SDIOM_WR_DMA_DONE_INT_STS_RAW 0h = Corresponding interrupt is inactive. 1h = Corresponding interrupt is active. Read is non-destructive. CC3235x Device Miscellaneous Registers SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 797 Table B-7. DMA_RIS Register Field Descriptions (continued) Field Type Reset Description SDIOMRD SDIOM_RD_DMA_DONE_INT_STS_RAW 0h = Corresponding interrupt is inactive. 1h = Corresponding interrupt is active. Read is non-destructive. SWRU543 – January 2019 CC3235x Device Miscellaneous Registers Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 798 GT_CCP[7-0]_TRIG_EN External trigger on GT_CCP[7-0] 0h = Disabled 1h = Enabled CC3235x Device Miscellaneous Registers SWRU543 – January 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
Page 799 TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2019, Texas Instruments Incorporated...

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