Texas Instruments CC3235 SimpleLink Series Technical Reference Manual page 328

Timer Registers
Table 9-14. GPTMRIS Register Field Descriptions (continued)
Bit Field
4 TAMRIS
3 RESERVED
2 CAERIS
1 CAMRIS
0 TATORIS
328
General-Purpose Timers
Type Reset Description
R X
GPTM Timer A Match Raw Interrupt. This bit is cleared by writing 1
to the TAMCINT bit in the GPTMICR register.
0h = The match value has not been reached.
1h = The TAMIE bit is set in the GPTMTAMR register, and the
match value in the GPTMTAMATCHR and (optionally)
GPTMTAPMR registers have been reached when configured in one-
shot or periodic mode.
R X
R X
GPTM Timer A Capture Mode Event Raw Interrupt. This bit is
cleared by writing 1 to the CAECINT bit in the GPTMICR register.
0h = The capture mode event for Timer A has not occurred.
1h = A capture mode event has occurred for Timer A. This interrupt
asserts when the subtimer is configured in input edge-time mode.
R X
GPTM Timer A Capture Mode Match Raw Interrupt. This bit is
cleared by writing 1 to the CAMCINT bit in the GPTMICR register.
0h = The capture mode match for Timer A has not occurred.
1h = A capture mode match has occurred for Timer A. This interrupt
asserts when the values in the GPTMTAR and GPTMTAPR match
the values in the GPTMTAMATCHR and GPTMTAPMR when
configured in input edge-time mode.
R X
GPTM Timer A Time-Out Raw Interrupt. This bit is cleared by writing
1 to the TATOCINT bit in the GPTMICR register.
0h = Timer A has not timed out.
1h = Timer A has timed out. This interrupt is asserted when a one-
shot or periodic mode timer reaches its count limit (0 or the value
loaded into GPTMTAILR, depending on the count direction).
Copyright © 2019, Texas Instruments Incorporated
www.ti.com
SWRU543 – January 2019
Submit Documentation Feedback