Slptmrcfg Register; Slptmrcfg Register Field Descriptions - Texas Instruments CC3235 SimpleLink Series Technical Reference Manual

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15.6.47 SLPTMRCFG Register (offset = 114h) [reset = 0h]
SLPTMRCFG is shown in
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bit Field
31-0 TMRCFG
SWRU543 – January 2019
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Figure 15-50 and described in
Figure 15-50. SLPTMRCFG Register
TMRCFG
R/W-0h
Table 15-50. SLPTMRCFG Register Field Descriptions
Type Reset
R/W 0h
Copyright © 2019, Texas Instruments Incorporated
Table 15-50.
9
Description
SLP_WAKE_TIMER_CFG Configuration (number of sysclks-80MHz)
for the Sleep wake-up timer.
Power, Reset, and Clock Management
PRCM Registers
8 7 6 5 4 3 2 1 0
577