Dma_Altset Register; Dma_Altset Register Field Descriptions - Texas Instruments CC3235 SimpleLink Series Technical Reference Manual

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4.3.4.13 DMA_ALTSET Register (offset = 30h) [reset = 0h]
DMA_ALTSET is shown in
Each bit of this register represents the corresponding DMA channel. Setting a bit configures the DMA
channel to use the alternate control data structure. Reading the register returns the status of which control
data structure is in use for the corresponding DMA channel. For Ping-Pong and Scatter-Gather cycle
types, the DMA controller automatically sets these bits to select the alternate channel control data
structure.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Bit Field
31-0 SET_n
SWRU543 – January 2019
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Figure 4-19 and described in
Figure 4-19. DMA_ALTSET Register
SET_n
W-0h
Table 4-23. DMA_ALTSET Register Field Descriptions
Type Reset
W 0h
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Table 4-23.
9
Description
Channel [n] Alternate Set
0h = DMA channel [n] is using the primary control structure
1h = DMA channel [n] is using the alternate control structure
Register Description
8 7 6 5 4 3 2 1
Direct Memory Access (DMA)
0
145