Dma_Enaclr Register; Dma_Enaclr Register Field Descriptions - Texas Instruments CC3235 SimpleLink Series Technical Reference Manual

Register Description
4.3.4.12 DMA_ENACLR Register (offset = 2Ch) [reset = 0h]
DMA_ENACLR is shown in
Each bit of this register represents the corresponding DMA channel. Setting a bit clears the corresponding
SET[n] bit in the DMAENASET register.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Bit Field
31-0 CLR_n
144
Direct Memory Access (DMA)
Figure 4-18 and described in
Figure 4-18. DMA_ENACLR Register
CLR_n
W-0h
Table 4-22. DMA_ENACLR Register Field Descriptions
Type Reset
W 0h
Copyright © 2019, Texas Instruments Incorporated
Table 4-22.
9
Description
Clear Channel [n] Enable Clear
0h = No effect
1h = Setting a bit clears the corresponding SET[n] bit in the
DMAENASET register meaning that channel [n] is disabled for DMA
transfers
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SWRU543 – January 2019
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