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CC3235SF SimpleLink
Texas Instruments CC3235SF SimpleLink Manuals
Manuals and User Guides for Texas Instruments CC3235SF SimpleLink. We have
2
Texas Instruments CC3235SF SimpleLink manuals available for free PDF download: Technical Reference Manual, User Manual
Texas Instruments CC3235SF SimpleLink Technical Reference Manual (799 pages)
Wi-Fi and Internet of Things
Brand:
Texas Instruments
| Category:
Microcontrollers
| Size: 5 MB
Table of Contents
List of Figures
14
Table of Contents
14
Register Bit Accessibility and Initial Condition
36
Cc32Xx MCU and Wi-Fi
41
System-On-Chip
41
Application CPU Block Diagram
52
TPIU Block Diagram
53
Summary of Processor Mode, Privilege Level, and Stack Use
54
Cortex -M4 Register Set
55
Processor Register Map
55
PSR Register Combinations
57
Memory Map
59
SRAM Memory Bit-Banding Regions
60
Data Storage
61
Exception Types
64
Cc32Xx Application Processor Interrupts
64
Vector Table
66
Exception Stack Frame
68
Fault Status and Fault Address Registers
70
Power-Management Architecture in Cc32Xx Soc
72
Core Peripheral Register Regions
78
Peripherals Register Map
80
Faults
82
Cortex ® -M4 Instruction Summary
83
Cortex Registers
83
ACTLR Register
84
ACTLR Register Field Descriptions
84
STCTRL Register
86
STCTRL Register Field Descriptions
86
STRELOAD Register
87
STRELOAD Register Field Descriptions
87
STCURRENT Register
88
STCURRENT Register Field Descriptions
88
0 To EN_6 Register
89
0 To EN_6 Register Field Descriptions
89
DIS_0 to DIS_6 Register
90
PEND_0 to PEND_6 Register
91
UNPEND_0 to UNPEND_6 Register
92
ACTIVE_0 to ACTIVE_6 Register
93
PRI_0 to PRI_49 Register
94
CPUID Register
95
CPUID Register Field Descriptions
95
INTCTRL Register
96
INTCTRL Register Field Descriptions
96
VTABLE Register
98
VTABLE Register Field Descriptions
98
APINT Register
99
APINT Register Field Descriptions
99
SYSCTRL Register
101
SYSCTRL Register Field Descriptions
101
CFGCTRL Register
102
CFGCTRL Register Field Descriptions
102
SYSPRI1 Register
104
SYSPRI2 Register
105
SYSPRI2 Register Field Descriptions
105
SYSPRI3 Register
106
SYSHNDCTRL Register
107
SYSHNDCTRL Register Field Descriptions
108
FAULTSTAT Register
110
FAULTSTAT Register Field Descriptions
111
HFAULTSTAT Register
114
FAULTDDR Register
115
FAULTDDR Register Field Descriptions
115
SWTRIG Register
116
SWTRIG Register Field Descriptions
116
DMA Channel Assignment
119
Channel Control Memory
121
Individual Control Structure
121
Ping-Pong Mode
123
Memory Scatter-Gather Mode
124
Peripheral Scatter-Gather Mode
125
Μdma Register Map
127
DM Registers
128
DMA_DSTENDP Register
129
DMA_SRCENDP Register Field Descriptions
129
DMA_DSTENDP Register Field Descriptions
129
DMA_SRCENDP Register
129
DMA_CHCTL Register
130
DMA_CHCTL Register Field Descriptions
130
DMA_(OFFSET_FROM_DMA_BASE_ADDRESS) Registers
132
DMA_STAT Register
133
DMA_STAT Register Field Descriptions
133
Reserved
133
R-X
133
DMA_CFG Register
134
DMA_CFG Register Field Descriptions
134
DMA_CTLBASE Register
135
DMA_CTLBASE Register Field Descriptions
135
DMA_ALTBASE Register
136
DMA_ALTBASE Register Field Descriptions
136
DMA_WAITSTAT Register
137
DMA_WAITSTAT Register Field Descriptions
137
DMA_SWREQ Register
138
DMA_SWREQ Register Field Descriptions
138
DMA_USEBURSTSET Register
139
DMA_USEBURSTSET Register Field Descriptions
139
DMA_USEBURSTCLR Register
140
DMA_USEBURSTCLR Register Field Descriptions
140
DMA_REQMASKSET Register
141
DMA_REQMASKSET Register Field Descriptions
141
DMA_REQMASKCLR Register
142
DMA_REQMASKCLR Register Field Descriptions
142
DMA_ENASET Register
143
DMA_ENASET Register Field Descriptions
143
DMA_ENACLR Register
144
DMA_ENACLR Register Field Descriptions
144
DMA_ALTSET Register
145
DMA_ALTSET Register Field Descriptions
145
DMA_ALTCLR Register
146
DMA_ALTCLR Register Field Descriptions
146
DMA_PRIOSET Register
147
DMA_PRIOSET Register Field Descriptions
147
DMA_PRIOCLR Register
148
DMA_PRIOCLR Register Field Descriptions
148
DMA_ERRCLR Register
149
DMA_CHASGN Register
150
DMA_CHASGN Register Field Descriptions
150
DMA_CHMAP0 Register
151
DMA_CHMAP1 Register
152
DMA_CHMAP2 Register
153
DMA_CHMAP3 Register
154
DMA_PV Register
155
Digital I/O Pads
157
GPIODATA Read Example
158
GPIO Pad Configuration Examples
160
GPIO Interrupt Configuration Examples
160
GPIO Registers
161
GPIODATA Write Example
158
GPIODATA Register
162
GPIODATA Register Field Descriptions
162
GPIODIR Register
163
GPIODIR Register Field Descriptions
163
GPIOIS Register
164
GPIOIS Register Field Descriptions
164
GPIOIBE Register
165
GPIOIBE Register Field Descriptions
165
GPIOIEV Register
166
GPIOIEV Register Field Descriptions
166
GPIOIM Register
167
GPIOIM Register Field Descriptions
167
GPIORIS Register
168
GPIORIS Register Field Descriptions
168
GPIOMIS Register
169
GPIOMIS Register Field Descriptions
169
GPIOICR Register
170
GPIOICR Register Field Descriptions
170
GPIO_TRIG_EN Register
171
GPIO Mapping
171
UART Module Block Diagram
175
UART Character Frame
176
Flow Control Mode
177
UART Registers
181
UARTDR Register
182
UARTDR Register Field Descriptions
182
UARTRSR_UARTECR Register
183
UARTRSR_UARTECR Register Field Descriptions
184
UARTFR Register
185
UARTFR Register Field Descriptions
185
UARTIBRD Register
187
UARTIBRD Register Field Descriptions
187
UARTFBRD Register
188
UARTFBRD Register Field Descriptions
188
UARTLCRH Register
189
UARTLCRH Register Field Descriptions
189
UARTCTL Register
191
UARTCTL Register Field Descriptions
191
UARTIFLS Register
193
UARTIM Register
194
UARTIM Register Field Descriptions
194
UARTRIS Register
196
UARTRIS Register Field Descriptions
196
UARTMIS Register
198
UARTMIS Register Field Descriptions
198
UARTICR Register
200
UARTICR Register Field Descriptions
200
UARTDMACTL Register
202
I2C Block Diagram
205
I2C Bus Configuration
206
I2C Signals (64QFN)
206
Complete Data Transfer with a 7-Bit Address
207
R/S Bit in First Byte
207
START and STOP Conditions
207
Data Validity During Bit Transfer on the I2C Bus
208
Timer Periods
210
Master Single TRANSMIT
214
Master Single RECEIVE
215
Master TRANSMIT of Multiple Data Bytes
216
Master RECEIVE of Multiple Data Bytes
217
Master RECEIVE with Repeated START after Master TRANSMIT
218
Master TRANSMIT with Repeated START after Master RECEIVE
219
Slave Command Sequence
220
I2C Registers
222
I2CMSA Register
223
I2CMSA Register Field Descriptions
223
I2CMCS Register
224
I2CMCS Register Field Descriptions
224
Write Field Decoding for I2CMCS[6:0]
226
I2CMDR Register
229
I2CMDR Register Field Descriptions
229
I2CMTPR Register
230
I2CMIMR Register
231
I2CMIMR Register Field Descriptions
231
I2CMRIS Register
233
I2CMRIS Register Field Descriptions
233
I2CMMIS Register
235
I2CMMIS Register Field Descriptions
235
I2CMICR Register
237
I2CMICR Register Field Descriptions
237
I2CMCR Register
239
I2CMCR Register Field Descriptions
239
I2CMCLKOCNT Register
240
I2CMCLKOCNT Register Field Descriptions
240
I2CMBMON Register
241
I2CMBMON Register Field Descriptions
241
I2CMBLEN Register
242
I2CMBLEN Register Field Descriptions
242
I2CMBCNT Register
243
I2CMBCNT Register Field Descriptions
243
I2CSOAR Register
244
I2CSOAR Register Field Descriptions
244
I2CSCSR Register
245
I2CSCSR Register Field Descriptions
245
I2CSDR Register
247
I2CSDR Register Field Descriptions
247
I2CSIMR Register
248
I2CSIMR Register Field Descriptions
248
I2CSRIS Register
250
I2CSRIS Register Field Descriptions
250
I2CSMIS Register
252
I2CSMIS Register Field Descriptions
252
I2CSICR Register
254
I2CSICR Register Field Descriptions
254
I2CSOAR2 Register
256
I2CSOAR2 Register Field Descriptions
256
I2CSACKCTL Register
257
I2CFIFODATA Register
258
I2CFIFODATA Register Field Descriptions
258
I2CFIFOCTL Register
259
I2CFIFOCTL Register Field Descriptions
259
I2CFIFOSTATUS Register
261
I2CPP Register
262
I2CPP Register Field Descriptions
262
I2CPC Register
263
I2CPC Register Field Descriptions
263
SPI Block Diagram
265
SPI Full-Duplex Transmission (Example)
267
Phase and Polarity Combinations
268
Full-Duplex Single Transfer Format with PHA
269
Full-Duplex Single Transfer Format with PHA
270
Contiguous Transfers with SPIEN Kept Active (Two Data Pins Interface Mode)
272
Clock Ratio Granularity
272
Granularity Examples
273
SPI Word Length WL
273
Transmit/Receive Mode with no FIFO Used
274
Transmit/Receive Mode with Only Receive FIFO Enabled
274
Transmit/Receive Mode with both FIFO Directions Used
275
Transmit/Receive Mode with Only Transmit FIFO Used
275
Buffer Almost Empty Level (AEL)
276
Buffer Almost Full Level (AFL)
276
Flow Chart - Module Initialization
283
Flow Chart - Common Transfer Sequence
284
Flow Chart - Transmit and Receive (Master and Slave)
285
Flow Chart - FIFO Mode Common Sequence (Master)
286
Flow Chart - FIFO Mode Transmit and Receive with Word Count (Master)
288
Flow Chart - FIFO Mode Transmit and Receive Without Word Count (Master)
289
SPI Registers
290
SPI_SYSCONFIG Register
291
SPI_SYSSTATUS Register
292
SPI_IRQSTATUS Register
293
SPI_IRQSTATUS Register Field Descriptions
294
SPI_IRQENABLE Register
295
SPI_MODULCTRL Register
296
SPI_CHCONF Register
297
SPI_CHCONF Register Field Descriptions
298
Spi
299
SPI_CHSTAT Register
300
SPI_CHSTAT Register Field Descriptions
300
SPI_CHCTRL Register
301
SPI_CHCTRL Register Field Descriptions
301
SPI_TX Register
302
SPI_TX Register Field Descriptions
302
SPI_RX Register
303
SPI_RX Register Field Descriptions
303
SPI_XFERLEVEL Register
304
SPI_XFERLEVEL Register Field Descriptions
304
GPTM Module Block Diagram
307
Available CCP Pins and PWM Outputs/Signals Pins
307
General-Purpose Timer Capabilities
308
Counter Values When the Timer Is Enabled in Periodic or One-Shot Modes
309
Counter Values When the Timer Is Enabled in Input Edge-Count Mode
310
Input Edge-Count Mode Example, Counting down
311
Counter Values When the Timer Is Enabled in Input Edge-Time Mode
312
Counter Values When the Timer Is Enabled in PWM Mode
313
Timer Registers
317
GPTMCFG Register
318
GPTMTAMR Register
319
GPTMTAMR Register Field Descriptions
319
GPTMTBMR Register
321
GPTMTBMR Register Field Descriptions
321
GPTMCTL Register
323
GPTMCTL Register Field Descriptions
323
GPTMIMR Register
325
GPTMIMR Register Field Descriptions
325
GPTMRIS Register
327
GPTMRIS Register Field Descriptions
327
GPTMMIS Register
329
GPTMMIS Register Field Descriptions
329
GPTMICR Register
331
GPTMICR Register Field Descriptions
331
GPTMTAILR Register
333
GPTMTAILR Register Field Descriptions
333
GPTMTBILR Register
334
GPTMTBILR Register Field Descriptions
334
GPTMTAMATCHR Register
335
GPTMTAMATCHR Register Field Descriptions
335
GPTMTBMATCHR Register
336
GPTMTBMATCHR Register Field Descriptions
336
GPTMTAPR Register
337
GPTMTAPR Register Field Descriptions
337
GPTMTBPR Register
338
GPTMTBPR Register Field Descriptions
338
GPTMTAPMR Register
339
GPTMTAPMR Register Field Descriptions
339
GPTMTBPMR Register
340
GPTMTBPMR Register Field Descriptions
340
GPTMTAR Register
341
GPTMTAR Register Field Descriptions
341
GPTMTBR Register
342
GPTMTBR Register Field Descriptions
342
GPTMTAV Register
343
GPTMTAV Register Field Descriptions
343
GPTMTBV Register
344
GPTMTBV Register Field Descriptions
344
GPTMDMAEV Register
345
GPTMDMAEV Register Field Descriptions
346
WDT Module Block Diagram
348
WATCHDOG Registers
350
WDTLOAD Register
351
WDTLOAD Register Field Descriptions
351
WDTVALUE Register
352
WDTVALUE Register Field Descriptions
352
WDTCTL Register
353
WDTCTL Register Field Descriptions
353
WDTICR Register
354
WDTICR Register Field Descriptions
354
WDTRIS Register
355
WDTRIS Register Field Descriptions
355
WDTTEST Register
356
WDTTEST Register Field Descriptions
356
WDTLOCK Register
357
WDTLOCK Register Field Descriptions
357
Watchdog Flow Chart
359
System Watchdog Recovery Sequence
360
Sdhost Controller Interface Block Diagram
363
Card Types
369
Throughput Data
370
Base Address of SD-Host (also Referred as MMCHS)
375
SD-HOST Registers
375
MMCHS_CSRE Register
376
MMCHS_CSRE Register Field Descriptions
376
MMCHS_CON Register
377
MMCHS_CON Register Field Descriptions
378
MMCHS_BLK Register
379
MMCHS_ARG Register
380
MMCHS_ARG Register Field Descriptions
380
MMCHS_CMD Register
381
MMCHS_CMD Register Field Descriptions
382
MMCHS_RSP10 Register
383
MMCHS_RSP10 Register Field Descriptions
383
MMCHS_RSP32 Register
384
MMCHS_RSP32 Register Field Descriptions
384
MMCHS_RSP54 Register
385
MMCHS_RSP54 Register Field Descriptions
385
MMCHS_RSP76 Register
386
MMCHS_RSP76 Register Field Descriptions
386
MMCHS_DATA Register
387
MMCHS_DATA Register Field Descriptions
387
MMCHS_PSTATE Register
388
MMCHS_PSTATE Register Field Descriptions
389
MMCHS_HCTL Register
390
MMCHS_SYSCTL Register
391
MMCHS_SYSCTL Register Field Descriptions
391
MMCHS_STAT Register
393
MMCHS_STAT Register Field Descriptions
394
MMCHS_IE Register
397
MMCHS_IE Register Field Descriptions
397
MMCHS_ISE Register
399
MMCHS_ISE Register Field Descriptions
399
I2S Protocol
402
I2S Module
403
Logical Clock Path
404
Ulintflags Parameter
411
Ulstatflags Parameter
412
I2S Registers Accessed through Peripheral Configuration Port
415
I2S Registers Accessed through DMA Port
416
I2S AFIFO Registers Accessed through Peripheral Configuration Port
416
AFIFOREV Register
417
AFIFOREV Register Field Descriptions
417
WFIFOCTL Register
418
WFIFOCTL Register Field Descriptions
418
PDIR Register
419
PDIR Register Field Descriptions
419
RFIFOCTL Register
421
RFIFOCTL Register Field Descriptions
421
RFIFOSTS Register
422
RFIFOSTS Register Field Descriptions
422
GBLCTL Register
423
GBLCTL Register Field Descriptions
423
RGBLCTL Register
425
RGBLCTL Register Field Descriptions
425
RMASK Register
427
RMASK Register Field Descriptions
427
RFMT Register
428
RFMT Register Field Descriptions
428
AFSRCTL Register
430
AFSRCTL Register Field Descriptions
430
RTDM Register
431
RTDM Register Field Descriptions
431
RINTCTL Register
432
RINTCTL Register Field Descriptions
432
RSTAT Register
434
RSTAT Register Field Descriptions
434
RSLOT Register
436
RSLOT Register Field Descriptions
436
REVTCTL Register
437
REVTCTL Register Field Descriptions
437
XGBLCTL Register
438
XGBLCTL Register Field Descriptions
438
XMASK Register
440
XMASK Register Field Descriptions
440
XFMT Register
441
XFMT Register Field Descriptions
441
AFSXCTL Register
443
AFSXCTL Register Field Descriptions
443
ACLKXCTL Register
444
ACLKXCTL Register Field Descriptions
444
AHCLKXCTL Register
445
XTDM Register
446
XTDM Register Field Descriptions
446
XINTCTL Register
447
XINTCTL Register Field Descriptions
447
XSTAT Register
449
XSTAT Register Field Descriptions
449
XSLOT Register
451
XSLOT Register Field Descriptions
451
XEVTCTL Register
452
XEVTCTL Register Field Descriptions
452
Srctln Registers
453
Srctln Register Field Descriptions
453
Xbufn Registers
455
Xbufn Register Field Descriptions
455
Rbufn Registers
456
Rbufn Register Field Descriptions
456
Analog-To-Digital Converter (Adc)
457
13.1 Overview
458
13.2 Key Features
458
Architecture of the ADC Module in Cc32Xx
458
Chapter 13
458
Operation of the ADC
459
ADC Registers
459
13.3 ADC Register Mapping
459
ADC_MODULE Registers
460
ADC_CTRL Register
461
ADC_CTRL Register Field Descriptions
461
ADC_MODULE Registers
461
ADC_CH0_IRQ_EN Register
462
ADC_CH2_IRQ_EN Register
463
ADC_CH4_IRQ_EN Register
464
ADC_CH6_IRQ_EN Register
465
ADC_CH0_IRQ_STATUS Register
466
ADC_CH2_IRQ_STATUS Register
467
ADC_CH4_IRQ_STATUS Register
468
ADC_CH6_IRQ_STATUS Register
469
ADC_DMA_MODE_EN Register
470
ADC_TIMER_CONFIGURATION Register
471
ADC_TIMER_CURRENT_COUNT Register
471
ADC_TIMER_CONFIGURATION Register Field Descriptions
471
ADC_TIMER_CURRENT_COUNT Register Field Descriptions
471
CHANNEL0FIFODATA Register
472
CHANNEL2FIFODATA Register
472
CHANNEL0FIFODATA Register Field Descriptions
472
CHANNEL2FIFODATA Register Field Descriptions
472
CHANNEL4FIFODATA Register
473
CHANNEL6FIFODATA Register
473
CHANNEL4FIFODATA Register Field Descriptions
473
CHANNEL6FIFODATA Register Field Descriptions
473
ADC_CH0_FIFO_LVL Register
474
ADC_CH2_FIFO_LVL Register
475
ADC_CH4_FIFO_LVL Register
476
ADC_CH6_FIFO_LVL Register
477
ADC_CH_ENABLE Register
478
Ulchannel Tags
479
13.5 Initialization and Configuration
479
13.6 Peripheral Library Apis for ADC Operation
479
Ulintflags Tags
480
Parallel Camera Interface Module
487
14.1 Overview
488
14.2 Image Sensor Interface
488
Camera Module Interfaces
488
Chapter 14
488
Synchronization Signals and Data Timing
489
Image Sensor Interface Signals
489
Synchronization Signals and Frame Timing
489
CAM_P_HS Toggles between Pixels in Decimation
490
FIFO Image Data Format
491
Ratio of the XCLK Frequency Generator
493
Parallel Camera Interface State Machine
491
Assertion and Deassertion of the DMA Request Signal
494
14.4 Programming Model
494
14.5 Interrupt Handling
495
Camera Registers
496
CC_SYSCONFIG Register
497
Cc_Sysconfig
497
CC_SYSSTATUS Register
498
Cc_Sysstatus
498
CC_IRQSTATUS Register
499
Cc_Irqstatus
499
CC_IRQSTATUS Register Field Descriptions
500
CC_IRQENABLE Register
501
Cc_Irqenable
501
CC_IRQENABLE Register Field Descriptions
502
CC_CTRL Register
503
CC_CTRL Register Field Descriptions
503
Cc_Ctrl
503
CC_CTRL_DMA Register
505
Cc_Ctrl_Dma
505
CC_CTRL_XCLK Register
506
Cc_Ctrl_Xclk
506
CC_FIFODATA Register
507
CC_FIFODATA Register Field Descriptions
507
14.7 Peripheral Library Apis
508
14.8 Developer's Guide
511
Power Management Unit Configuration
517
Sleep Modes
519
Possible PM State Combinations of Application Processor and Network Subsystem (NWP+WLAN)
520
Power Management Control Architecture in Cc32Xx
521
Peripheral Macro Table
529
PRCM Registers
529
CAMCLKCFG Register
531
CAMCLKEN Register
532
CAMCLKEN Register Field Descriptions
532
CAMSWRST Register
533
CAMSWRST Register Field Descriptions
533
MCASPCLKEN Register
534
MCASPSWRST Register
535
SDIOMCLKCFG Register
536
SDIOMCLKEN Register
537
SDIOMSWRST Register
538
APSPICLKCFG Register
539
APSPICLKCFG Register Field Descriptions
539
APSPICLKEN Register
540
APSPISWRST Register
541
DMACLKEN Register
542
DMACLKEN Register Field Descriptions
542
DMASWRST Register
543
GPIO0CLKEN Register
544
GPIO0SWRST Register
545
GPIO1CLKEN Register
546
GPIO1SWRST Register
547
GPIO2CLKEN Register
548
GPIO2SWRST Register
549
GPIO3CLKEN Register
550
GPIO3SWRST Register
551
GPIO4CLKEN Register
552
GPIO4SWRST Register
553
WDTCLKEN Register
554
WDTCLKEN Register Field Descriptions
554
WDTSWRST Register
555
UART0CLKEN Register
556
UART0SWRST Register
557
UART1CLKEN Register
558
UART1SWRST Register
559
GPT0CLKCFG Register
560
GPT0SWRST Register
561
GPT1CLKEN Register
562
GPT1SWRST Register
563
GPT2CLKEN Register
564
GPT2SWRST Register
565
GPT3CLKEN Register
566
GPT3SWRST Register
567
MCASPCLKCFG0 Register
568
MCASPCLKCFG1 Register
569
I2CLCKEN Register
570
I2CLCKEN Register Field Descriptions
570
I2CSWRST Register
571
I2CSWRST Register Field Descriptions
571
LPDSREQ Register
572
LPDSREQ Register Field Descriptions
572
TURBOREQ Register
573
TURBOREQ Register Field Descriptions
573
DSLPWAKECFG Register
574
DSLPTIMRCFG Register
575
DSLPTIMRCFG Register Field Descriptions
575
SLPWAKEEN Register
576
SLPTMRCFG Register
577
SLPTMRCFG Register Field Descriptions
577
WAKENWP Register
578
WAKENWP Register Field Descriptions
578
RCM_IS Register
579
RCM_IS Register Field Descriptions
579
RCM_IEN Register
580
RCM_IEN Register Field Descriptions
580
I\/O Pads and Pin Multiplexing
581
16.1 Overview
582
GPIO Pin Electrical Specifications (25°C) (Except Pins 29, 30, 45, 50, 52, 53)
583
GPIO Pin Electrical Specifications (25°C) for Pins
583
Pin Internal Pullup and Pulldown Electrical Specifications (25°C)
583
Chapter 16
582
16.2 I/O Pad Electrical Specifications
583
16.3 Analog and Digital Pin Multiplexing
584
16.4 Special Analog/Digital Pins
584
Board Configuration to Use Pins 45 and 52
586
Analog Mux Control Registers and Bits
587
Board-Level Behavior
588
Gpio/Pins Available for Application
589
16.6 Pins Available for Applications
589
Pin Multiplexing
592
Pin Groups for Audio Interface (I2S)
603
Pin Groups for SPI Interface (GSPI)
603
Pin Groups for SD-Card Interface
603
16.8 Pin Mapping Recommendations
603
Pad Configuration Registers
604
GPIO_PAD_CONFIG_0 to GPIO_PAD_CONFIG_32 Register Description
605
Reserved
605
I/O Pad Data and Control Path Architecture in Cc32Xx
606
Recommended Pin Multiplexing Configurations
607
R-X
607
Wake on Pad for Hibernate Mode
609
Sense-On-Power Configurations
610
AES Block Diagram
613
Key-Block-Round Combinations
615
AES - ECB Feedback Mode
616
AES - CBC Feedback Mode
617
AES Encryption with CTR/ICM Mode
618
AES - CFB Feedback Mode
619
AES - F8 Mode
620
AES - XTS Operation
621
AES - F9 Operation
622
AES - CBC-MAC Authentication Mode
623
AES - GCM Operation
624
AES - CCM Operation
625
Interrupts and Events
626
AES Polling Mode
629
AES Interrupt Service
631
AES Registers
632
AES_KEY2_6 Register
633
AES_KEY2_7 Register
633
AES_KEY2_6 Register Field Descriptions
633
AES_KEY2_7 Register Field Descriptions
633
AES_KEY2_4 Register
634
AES_KEY2_5 Register
634
AES_KEY2_4 Register Field Descriptions
634
AES_KEY2_5 Register Field Descriptions
634
AES_KEY2_2 Register
635
AES_KEY2_3 Register
635
AES_KEY2_2 Register Field Descriptions
635
AES_KEY2_3 Register Field Descriptions
635
AES_KEY2_0 Register
636
AES_KEY2_1 Register
636
AES_KEY2_0 Register Field Descriptions
636
AES_KEY2_1 Register Field Descriptions
636
AES_KEY1_6 Register
637
AES_KEY1_7 Register
637
AES_KEY1_6 Register Field Descriptions
637
AES_KEY1_7 Register Field Descriptions
637
AES_KEY1_4 Register
638
AES_KEY1_5 Register
638
AES_KEY1_4 Register Field Descriptions
638
AES_KEY1_5 Register Field Descriptions
638
AES_KEY1_2 Register
639
AES_KEY1_3 Register
639
AES_KEY1_2 Register Field Descriptions
639
AES_KEY1_3 Register Field Descriptions
639
AES_KEY1_0 Register
640
AES_KEY1_1 Register
640
AES_KEY1_0 Register Field Descriptions
640
AES_KEY1_1 Register Field Descriptions
640
AES_IV_IN_0 Register
641
AES_IV_IN_1 Register
641
AES_IV_IN_0 Register Field Descriptions
641
AES_IV_IN_1 Register Field Descriptions
641
AES_IV_IN_2 Register
642
AES_IV_IN_3 Register
642
AES_IV_IN_2 Register Field Descriptions
642
AES_IV_IN_3 Register Field Descriptions
642
AES_CTRL Register
643
AES_CTRL Register Field Descriptions
643
AES_C_LENGTH_0 Register
646
AES_C_LENGTH_0 Register Field Descriptions
646
AES_C_LENGTH_1 Register
647
Reserved R-X
647
AES_AUTH_LENGTH Register
648
AES_AUTH_LENGTH Register Field Descriptions
648
AES_DATA_IN_0 Register
649
AES_DATA_IN_1 Register
649
AES_DATA_IN_0 Register Field Descriptions
649
AES_DATA_IN_1 Register Field Descriptions
649
AES_DATA_IN_2 Register
650
AES_DATA_IN_3 Register
650
AES_DATA_IN_2 Register Field Descriptions
650
AES_DATA_IN_3 Register Field Descriptions
650
AES_TAG_OUT_0 Register
651
AES_TAG_OUT_1 Register
651
AES_TAG_OUT_0 Register Field Descriptions
651
AES_TAG_OUT_1 Register Field Descriptions
651
AES_TAG_OUT_2 Register
652
AES_TAG_OUT_3 Register
652
AES_TAG_OUT_2 Register Field Descriptions
652
AES_TAG_OUT_3 Register Field Descriptions
652
AES_REVISION Register
653
Reserved R-X
653
AES_REVISION Register Field Descriptions
654
AES_SYSCONFIG Register
655
R/W-0H
655
AES_IRQSTATUS Register
656
AES_IRQENABLE Register
657
CRYPTOCLKEN Register
658
DTHE_AES_IM Register
659
DTHE_AES_RIS Register
660
DTHE_AES_MIS Register
661
DTHE_AES_IC Register
662
Key Repartition
664
DES Block Diagram
665
DES - ECB Feedback Mode
667
DES3DES - CBC Feedback Mode
667
DES3DES - CFB Feedback Mode
668
DES Global Initialization
668
DES Algorithm Type Configuration
668
3DES Algorithm Type Configuration
669
DES Polling Mode
670
DES Interrupt Service
671
DES Interrupt Mode
671
DES DMA Mode
671
DES Context Input Event Service
672
DES Register Map
673
DTHE_DES_IM Register
674
DTHE_DES_RIS Register
675
DTHE_DES_MIS Register
676
DTHE_DES_IC Register
677
DES_KEY3_L Register
678
DES_KEY3_L Register Field Descriptions
678
DES_KEY3_H Register
679
DES_KEY3_H Register Field Descriptions
679
DES_KEY2_L Register
680
DES_KEY2_L Register Field Descriptions
680
DES_KEY2_H Register
681
DES_KEY2_H Register Field Descriptions
681
DES_KEY1_L Register
682
DES_KEY1_L Register Field Descriptions
682
DES_KEY1_H Register
683
DES_KEY1_H Register Field Descriptions
683
DES_IV_L Register
684
DES_IV_L Register Field Descriptions
684
DES_IV_H Register
685
DES_IV_H Register Field Descriptions
685
DES_CTRL Register
686
DES_CTRL Register Field Descriptions
686
DES_LENGTH Register
687
DES_LENGTH Register Field Descriptions
687
DES_DATA_L Register
688
DES_DATA_L Register Field Descriptions
688
DES_DATA_H Register
689
DES_DATA_H Register Field Descriptions
689
DES_SYSCONFIG Register
690
DES_SYSCONFIG Register Field Descriptions
690
DES_IRQSTATUS Register
691
DES_IRQENABLE Register
692
SHA/MD5 Module Block Diagram
694
Interrupts and Events
695
SHA/MD5 Module Algorithm Selection
696
Outer Digest Registers
697
Inner Digest Registers
697
SHA Digest Processed in Three Passes
699
SHA Digest Processed in One Pass
700
Continuing a Prior HMAC
702
SHA/MD5 Polling Mode
703
Interrupt Mode
703
DMA Mode
703
SHA/MD5 Interrupt Subroutine
704
SHA-MD5 Registers
705
Overview of Public World, Inner and Outer Digest Registers, and Usage for MD5, SHA-1, and SHA
706
SHAMD5_ODIGEST_A Register
708
SHAMD5_ODIGEST_A Register Field Descriptions
708
SHAMD5_ODIGEST_B Register
709
SHAMD5_ODIGEST_B Register Field Descriptions
709
SHAMD5_ODIGEST_C Register
710
SHAMD5_ODIGEST_C Register Field Descriptions
710
SHAMD5_ODIGEST_D Register
711
SHAMD5_ODIGEST_D Register Field Descriptions
711
SHAMD5_ODIGEST_E Register
712
SHAMD5_ODIGEST_E Register Field Descriptions
712
SHAMD5_ODIGEST_F Register
713
SHAMD5_ODIGEST_F Register Field Descriptions
713
SHAMD5_ODIGEST_G Register
714
SHAMD5_ODIGEST_G Register Field Descriptions
714
SHAMD5_ODIGEST_H Register
715
SHAMD5_ODIGEST_H Register Field Descriptions
715
SHAMD5_IDIGEST_A Register
716
SHAMD5_IDIGEST_A Register Field Descriptions
716
SHAMD5_IDIGEST_B Register
717
SHAMD5_IDIGEST_B Register Field Descriptions
717
SHAMD5_IDIGEST_C Register
718
SHAMD5_IDIGEST_C Register Field Descriptions
718
SHAMD5_IDIGEST_D Register
719
SHAMD5_IDIGEST_D Register Field Descriptions
719
SHAMD5_IDIGEST_E Register
720
SHAMD5_IDIGEST_E Register Field Descriptions
720
SHAMD5_IDIGEST_F Register
721
SHAMD5_IDIGEST_F Register Field Descriptions
721
SHAMD5_IDIGEST_G Register
722
SHAMD5_IDIGEST_G Register Field Descriptions
722
SHAMD5_IDIGEST_H Register
723
SHAMD5_IDIGEST_H Register Field Descriptions
723
SHAMD5_DIGEST_COUNT Register
724
SHAMD5_DIGEST_COUNT Register Field Descriptions
724
SHAMD5_MODE Register
725
SHAMD5_MODE Register Field Descriptions
726
SHAMD5_LENGTH Register
727
SHAMD5_LENGTH Register Field Descriptions
727
SHAMD5_DATA0_IN Register
729
SHAMD5_DATA0_IN Register Field Descriptions
729
SHAMD5_DATA1_IN Register
730
SHAMD5_DATA1_IN Register Field Descriptions
730
SHAMD5_DATA2_IN Register
731
SHAMD5_DATA2_IN Register Field Descriptions
731
SHAMD5_DATA3_IN Register
732
SHAMD5_DATA3_IN Register Field Descriptions
732
SHAMD5_DATA4_IN Register
733
SHAMD5_DATA4_IN Register Field Descriptions
733
SHAMD5_DATA5_IN Register
734
SHAMD5_DATA5_IN Register Field Descriptions
734
SHAMD5_DATA6_IN Register
735
SHAMD5_DATA6_IN Register Field Descriptions
735
SHAMD5_DATA7_IN Register
736
SHAMD5_DATA7_IN Register Field Descriptions
736
SHAMD5_DATA8_IN Register
737
SHAMD5_DATA8_IN Register Field Descriptions
737
SHAMD5_DATA9_IN Register
738
SHAMD5_DATA9_IN Register Field Descriptions
738
SHAMD5_DATA10_IN Register
739
SHAMD5_DATA10_IN Register Field Descriptions
739
SHAMD5_DATA11_IN Register
740
SHAMD5_DATA11_IN Register Field Descriptions
740
SHAMD5_DATA12_IN Register
741
SHAMD5_DATA12_IN Register Field Descriptions
741
SHAMD5_DATA13_IN Register
742
SHAMD5_DATA13_IN Register Field Descriptions
742
SHAMD5_DATA14_IN Register
743
SHAMD5_DATA14_IN Register Field Descriptions
743
SHAMD5_DATA15_IN Register
744
SHAMD5_DATA15_IN Register Field Descriptions
744
SHAMD5_SYSCONFIG Register
745
SHAMD5_IRQSTATUS Register
746
SHAMD5_IRQENABLE Register
747
DTHE_SHA_IM Register
748
DTHE_SHA_RIS Register
749
DTHE_SHA_MIS Register
750
DTHE_SHA_IC Register
751
Endian Configuration
754
Endian Configuration with Bit Reversal
754
CRC Registers
756
CRCCTRL Register
757
CRCCTRL Register Field Descriptions
757
Bit Field
757
CRCSEED Register
759
CRCSEED Register Field Descriptions
759
CRCDIN Register
760
CRCDIN Register Field Descriptions
760
CRCRSLTPP Register
761
CRCRSLTPP Register Field Descriptions
761
Flash Registers
765
FMA Register
766
FMA Register Field Descriptions
766
FMD Register
767
FMD Register Field Descriptions
767
FMC Register
768
FMC Register Field Descriptions
768
FCRIS Register
770
FCRIS Register Field Descriptions
770
FCIM Register
772
FCIM Register Field Descriptions
772
FCMISC Register
773
FCMISC Register Field Descriptions
773
FMC2 Register
775
FMC2 Register Field Descriptions
775
FWBVAL Register
776
FWBVAL Register Field Descriptions
776
Fwbn Register
777
Fwbn Register Field Descriptions
777
CC3235SF Boot Flow
778
Flash Memory Partition
779
User Application Image Binary Structure on Serial Flash
780
On-Chip Flash Programming and Update
782
Flash Debug Image Layout
783
Peripheral Samples
784
Cc3235X Device Miscellaneous Register Summary
785
DMA_IMR Register
786
DMA_IMR Register Field Descriptions
786
Type Reset Description RX
786
DMA_IMS Register
788
DMA_IMS Register Field Descriptions
788
R/W 0H
788
DMA_IMC Register
790
DMA_IMC Register Field Descriptions
790
DMA_ICR Register
792
DMA_ICR Register Field Descriptions
792
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Texas Instruments CC3235SF SimpleLink User Manual (27 pages)
Brand:
Texas Instruments
| Category:
Microcontrollers
| Size: 3 MB
Table of Contents
Table of Contents
1
Default I 2 C Addresses (of Onboard Sensors)
2
Introduction
3
Key Features
3
Kit Contents
3
Regulatory Compliance
4
Hardware Description
5
Block Diagram
6
Hardware Features
7
Pin 1 Marking on CC3235 Launchpad™ (3V3 Tag)
8
JTAG Header Pin Definitions
9
C Connections
11
C Jumper Definitions
11
Jumper Settings for Launchpad™ Power
12
External Supply Connections and LED Enable Jumper
13
Reset Pull-Up Jumper
13
SOP Jumpers (Default Setting Shown)
14
J15, J16, J17 on Launchpad
14
UART Routed to USB COM Port
15
UART Routed to 20-Pin Header Connector
15
Push-Button Definitions
16
LED Indicators
16
CC3235 Boosterpack™ Header Pin Assignments
17
Powering from USB Jumper Settings
18
CC3235 Launchpad™ Powered by Battery
19
Only CC3235 Device and Serial Flash Powered by Battery
20
Low-Current Measurement (<1 Ma)
21
Active Power Measurements (>1 Ma)
22
Using Onboard Antenna (Default Condition)
23
Board Modified for External Antenna Connections (Measure 2.4 Ghz)
23
Board Modified for External Antenna Connections (Measure 2.4 Ghz or 5 Ghz)
24
CC3235SF Launchpad™ Top-Layer Assembly Drawing
25
CC3235S Launchpad™ Top-Layer Assembly Drawing
26
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