Mcaspclken Register - Texas Instruments CC3235 SimpleLink Series Technical Reference Manual

PRCM Registers
15.6.4 MCASPCLKEN Register (offset = 14h) [reset = 0h]
MCASPCLKEN is shown in
31 30
23 22
15 14
7 6
Bit Field
31-24 RESERVED
23-17 NU1
16 DSLPCLKEN
15-9 NU2
8 SLPCLKEN
7-1 NU3
0 RUNCLKEN
534
Power, Reset, and Clock Management
Figure 15-7 and described in
Figure 15-7. MCASPCLKEN Register
29 28
RESERVED
R-0h
21 20
NU1
R-0h
13 12
NU2
R-0h
5 4
NU3
R-0h
Table 15-7. MCASPCLKEN Register Field Descriptions
Type Reset
R 0h
R 0h
R 0h
R 0h
R/W 0h
R 0h
R/W 0h
Copyright © 2019, Texas Instruments Incorporated
Table 15-7.
27 26
19 18
11 10
3 2
Description
MCASP_DSLP_CLK_ENABLE
0h = Disable MCASP clock during deep-sleep mode
MCASP_SLP_CLK_ENABLE
0h = Disable MCASP clock during sleep mode
1h = Enable MCASP clock during sleep mode
MCASP_RUN_CLK_ENABLE
0h = Disable MCASP clock during run mode
1h = Enable MCASP clock during run mode
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25 24
17 16
DSLPCLKEN
R-0h
9 8
SLPCLKEN
R/W-0h
1 0
RUNCLKEN
R/W-0h
SWRU543 – January 2019
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