Aes_Irqenable Register - Texas Instruments CC3235 SimpleLink Series Technical Reference Manual

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17.4.36 AES_IRQENABLE Register (Offset = 90h) [reset = X]
AES_IRQENABLE is shown in
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This register contains an enable bit for each unique interrupt generated by the module. It matches the
layout of AES_IRQSTATUS register. An interrupt is enabled when the bit in this register is set to 1. An
interrupt that is enabled is propagated to the SINTREQUEST_x output. All interrupts must be enabled
explicitly by writing this register.
31 30
23 22
15 14
7 6
RESERVED
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Bit Field
31-4 RESERVED
3 CONTEXT_OUT
2 DATA_OUT
1 DATA_IN
0 CONTEXT_IN
SWRU543 – January 2019
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Figure 17-49 and described in
Table.
Figure 17-49. AES_IRQENABLE Register
29 28
21 20
13 12
5 4
R-X
Table 17-39. AES_IRQENABLE Register Field Descriptions
Type Reset
R X
R/W 0h
R/W 0h
R/W 0h
R/W 0h
Copyright © 2019, Texas Instruments Incorporated
Table 17-39.
27
RESERVED
R-X
19
RESERVED
R-X
11
RESERVED
R-X
3
CONTEXT_OU DATA_OUT
T
R/W-0h R/W-0h
Description
This bit indicates authentication tag (and IV) interrupts are active,
and triggers the interrupt output.
This bit indicates data output interrupt is active, and triggers the
interrupt output
This bit indicates data input interrupt is active, and triggers the
interrupt output
This bit indicates context interrupt is active, and triggers the interrupt
output.
Advance Encryption Standard Accelerator (AES)
AES Registers
26 25
18 17
10 9
2 1
DATA_IN CONTEXT_IN
R/W-0h
24
16
8
0
R/W-0h
657