DMA_IMS Register (offset = 90h) [reset = 0h]
B.2
DMA_IMS Register (offset = 90h) [reset = 0h]
Register mask: FF0Fh
DMA_IMS is shown in
31
30
23
22
15
14
ADCWR
7
6
RESERVED
Bit
Field
31-16
RESERVED
15-12
ADCWR
11
MCASPWR
10
MCASPRD
9
CAMEMPT
8
CAMFULL
7-4
RESERVED
3
APSPIWR
2
APSPIRD
1
SDIOMWR
788
CC3235x Device Miscellaneous Registers
Figure B-2
and described in
Figure B-2. DMA_IMS Register
29
28
21
20
13
12
R/W-0h
5
4
R-X
Table B-3. DMA_IMS Register Field Descriptions
Type
Reset
R
X
R/W
0h
R/W
0h
R/W
0h
R/W
0h
R/W
0h
R
X
R/W
0h
R/W
0h
R/W
0h
Copyright © 2019, Texas Instruments Incorporated
Table
B-3.
27
RESERVED
R-X
19
RESERVED
R-X
11
MCASPWR
MCASPRD
R/W-0h
R/W-0h
3
APSPIWR
APSPIRD
R/W-0h
R/W-0h
Description
ADC_WR_DMA_DONE_INT_MASK_SET
bit 15: ADC channel 6 DMA Done IRQ
bit 14: ADC channel 4 DMA Done IRQ
bit 13: ADC channel 2 DMA Done IRQ
bit 12: ADC channel 0 DMA Done IRQ
0h = No effect
1h = Set mask of the corresponding DMA DONE IRQ
MCASP_WR_DMA_DONE_INT_MASK_SET
0h = No effect
1h = Set mask of the corresponding DMA DONE IRQ
MCASP_RD_DMA_DONE_INT_MASK_SET
0h = No effect
1h = Set mask of the corresponding DMA DONE IRQ
CAM_FIFO_EMPTY_DMA_DONE_INT_MASK_SET
0h = No effect
1h = Set mask of the corresponding DMA DONE IRQ
CAM_THRESHHOLD_DMA_DONE_INT_MASK_SET
0h = No effect
1h = Set mask of the corresponding DMA DONE IRQ
APPS_SPI_WR_DMA_DONE_INT_MASK_SET
0h = No effect
1h = Set mask of the corresponding DMA DONE IRQ
APPS_SPI_RD_DMA_DONE_INT_MASK_SET
0h = No effect
1h = Set mask of the corresponding DMA DONE IRQ
SDIOM_WR_DMA_DONE_INT_MASK_SET
0h = No effect
1h = Set mask of the corresponding DMA DONE IRQ
26
25
18
17
10
9
CAMEMPT
R/W-0h
2
1
SDIOMWR
R/W-0h
SWRU543 – January 2019
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24
16
8
CAMFULL
R/W-0h
0
SDIOMRD
R/W-0h
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