Texas Instruments CC3235 SimpleLink Series Technical Reference Manual page 12

19.1.2 µDMA and Interrupt Requests
19.1.3 Operation Description
19.1.4 SHA/MD5 Programming Guide
19.2 SHA-MD5 Registers
19.2.1 SHAMD5_ODIGEST_A Register (Offset = 0h) [reset = 0h]
19.2.2 SHAMD5_ODIGEST_B Register (Offset = 4h) [reset = 0h]
19.2.3 SHAMD5_ODIGEST_C Register (Offset = 8h) [reset = 0h]
19.2.4 SHAMD5_ODIGEST_D Register (Offset = Ch) [reset = 0h]
19.2.5 SHAMD5_ODIGEST_E Register (Offset = 10h) [reset = 0h]
19.2.6 SHAMD5_ODIGEST_F Register (Offset = 14h) [reset = 0h]
19.2.7 SHAMD5_ODIGEST_G Register (Offset = 18h) [reset = 0h]
19.2.8 SHAMD5_ODIGEST_H Register (Offset = 1Ch) [reset = 0h]
19.2.9 SHAMD5_IDIGEST_A Register (Offset = 20h) [reset = 0h]
19.2.10 SHAMD5_IDIGEST_B Register (Offset = 24h) [reset = 0h]
19.2.11 SHAMD5_IDIGEST_C Register (Offset = 28h) [reset = 0h]
19.2.12 SHAMD5_IDIGEST_D Register (Offset = 2Ch) [reset = 0h]
19.2.13 SHAMD5_IDIGEST_E Register (Offset = 30h) [reset = 0h]
19.2.14 SHAMD5_IDIGEST_F Register (Offset = 34h) [reset = 0h]
19.2.15 SHAMD5_IDIGEST_G Register (Offset = 38h) [reset = 0h]
19.2.16 SHAMD5_IDIGEST_H Register (Offset = 3Ch) [reset = 0h]
19.2.17 SHAMD5_DIGEST_COUNT Register (Offset = 40h) [reset = 0h]
19.2.18 SHAMD5_MODE Register (Offset = 44h) [reset = X]
19.2.19 SHAMD5_LENGTH Register (Offset = 48h) [reset = 0h]
19.2.20 SHAMD5_DATA0_IN Register (Offset = 80h) [reset = 0h]
19.2.21 SHAMD5_DATA1_IN Register (Offset = 84h) [reset = 0h]
19.2.22 SHAMD5_DATA2_IN Register (Offset = 88h) [reset = 0h]
19.2.23 SHAMD5_DATA3_IN Register (Offset = 8Ch) [reset = 0h]
19.2.24 SHAMD5_DATA4_IN Register (Offset = 90h) [reset = 0h]
19.2.25 SHAMD5_DATA5_IN Register (Offset = 94h) [reset = 0h]
19.2.26 SHAMD5_DATA6_IN Register (Offset = 98h) [reset = 0h]
19.2.27 SHAMD5_DATA7_IN Register (Offset = 9Ch) [reset = 0h]
19.2.28 SHAMD5_DATA8_IN Register (Offset = A0h) [reset = 0h]
19.2.29 SHAMD5_DATA9_IN Register (Offset = A4h) [reset = 0h]
19.2.30 SHAMD5_DATA10_IN Register (Offset = A8h) [reset = 0h]
19.2.31 SHAMD5_DATA11_IN Register (Offset = ACh) [reset = 0h]
19.2.32 SHAMD5_DATA12_IN Register (Offset = B0h) [reset = 0h]
19.2.33 SHAMD5_DATA13_IN Register (Offset = B4h) [reset = 0h]
19.2.34 SHAMD5_DATA14_IN Register (Offset = B8h) [reset = 0h]
19.2.35 SHAMD5_DATA15_IN Register (Offset = BCh) [reset = 0h]
19.2.36 SHAMD5_SYSCONFIG Register (Offset = 110h) [reset = X]
19.2.37 SHAMD5_IRQSTATUS Register (Offset = 118h) [reset = X]
19.2.38 SHAMD5_IRQENABLE Register (Offset = 11Ch) [reset = X]
19.2.39 DTHE_SHA_IM Register (Offset = 810h) [reset = X]
19.2.40 DTHE_SHA_RIS Register (Offset = 814h) [reset = X]
19.2.41 DTHE_SHA_MIS Register (Offset = 818h) [reset = X]
19.2.42 DTHE_SHA_IC Register (Offset = 81Ch) [reset = X]
20 Cyclical Redundancy Check (CRC)
20.1 Functional Description
20.1.1 CRC Support
20.2 Initialization and Configuration
20.2.1 CRC Initialization and Configuration
20.3 CRC Registers
20.3.1 CRCCTRL Register (Offset = C00h) [reset = 0h]
12
Contents
................................................................................
..........................................................................................
...............................................................................
......................................................................................................
.....................................................................................
....................................................................................................
....................................................................................................
..........................................................................................
............................................................................................................
Copyright © 2019, Texas Instruments Incorporated
...............................................
...............................................
...............................................
..............................................
.............................................
.............................................
.............................................
.............................................
...............................................
.............................................
.............................................
............................................
.............................................
.............................................
.............................................
............................................
....................................................
................................................
..............................................
..............................................
..............................................
..............................................
..............................................
..............................................
..............................................
..............................................
..............................................
..............................................
............................................
............................................
............................................
............................................
............................................
............................................
...........................................
...........................................
...........................................
.....................................................
...................................................
...................................................
.....................................................
.........................................................................
...........................................................
www.ti.com
......................................
SWRU543 – January 2019
Submit Documentation Feedback
695
695
701
705
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
727
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
753
755
755
756
757