Texas Instruments CC3235 SimpleLink Series Technical Reference Manual page 3

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3.3.1 Cortex Registers
4 Direct Memory Access (DMA)
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4.1 Overview
4.2 Functional Description
4.2.1 Channel Assignment
4.2.2 Priority
4.2.3 Arbitration Size
4.2.4 Channel Configuration
4.2.5 Transfer Mode
4.2.6 Transfer Size and Increment
4.2.7 Peripheral Interface
4.2.8 Interrupts and Errors
4.3 Register Description
4.3.1 DMA Register Map
4.3.2 µDMA Channel Control Structure
4.3.3 DMA Registers
4.3.4 DMA_(OFFSET_FROM_DMA_BASE_ADDRESS) Registers
5 General-Purpose Input/Outputs (GPIOs)
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5.1 Overview
5.2 Functional Description
5.2.1 Data Control
5.3 Interrupt Control
5.3.1 µDMA Trigger Source
5.4 Initialization and Configuration
5.5 GPIO Registers
5.5.1 GPIODATA Register (offset = 0h) [reset = 0h]
5.5.2 GPIODIR Register (offset = 400h) [reset = 0h]
5.5.3 GPIOIS Register (offset = 404h) [reset = 0h]
5.5.4 GPIOIBE Register (offset = 408h) [reset = 0h]
5.5.5 GPIOIEV Register (offset = 40Ch) [reset = 0h]
5.5.6 GPIOIM Register (offset = 410h) [reset = 0h]
5.5.7 GPIORIS Register (offset = 414h) [reset = 0h]
5.5.8 GPIOMIS Register (offset = 418h) [reset = 0h]
5.5.9 GPIOICR Register (offset = 41Ch) [reset = 0h]
5.5.10 GPIO_TRIG_EN Register
6 Universal Asynchronous Receivers/Transmitters (UARTs)
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6.1 Overview
6.1.1 Block Diagram
6.2 Functional Description
6.2.1 Transmit and Receive Logic
6.2.2 Baud-Rate Generation
6.2.3 Data Transmission
6.2.4 Initialization and Configuration
6.3 UART Registers
6.3.1 UARTDR Register (Offset = 0h) [reset = 0h]
6.3.2 UARTRSR_UARTECR Register (Offset = 4h) [reset = 0h]
6.3.3 UARTFR Register (Offset = 18h) [reset = 90h]
6.3.4 UARTIBRD Register (Offset = 24h) [reset = 0h]
6.3.5 UARTFBRD Register (Offset = 28h) [reset = 0h]
6.3.6 UARTLCRH Register (Offset = 2Ch) [reset = 0h]
6.3.7 UARTCTL Register (Offset = 30h) [reset = 300h]
6.3.8 UARTIFLS Register (Offset = 34h) [reset = 12h]
SWRU543 – January 2019
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Copyright © 2019, Texas Instruments Incorporated
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