Status Byte And Service Request (Srq) - ITech IT8800 Series Programming Manual

registers:
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The IT8800 Series status model shows how the two queues are structured with
the other registers.
Output queue
The output queue holds data that are related to the normal operation of the
instrument. For example, when a query command is sent, the response
message is placed on the output queue.
When data is placed in the output queue, the Message Available (MAV) bit in
the status byte register sets. A data message is cleared from the output queue
when it is read. The output queue is considered cleared when it is empty. An
empty output queue clears the MAV bit in the status byte register.
You can read a message from the output queue after a query is sent.
Error queue
The error queue holds error and status messages. When an error or status
event occurs, a message that defines the error/status is placed in the error
queue. This queue holds up to 32 messages.
When a message is placed in the error queue, the Error Available (EAV) bit in
the status byte register is set. An error message is cleared from the error/status
queue when it is read. The error queue is considered cleared when it is empty.
An empty error queue clears the EAV bit in the status byte register. Read an
error message from the error queue by sending :SYSTem:ERRor?command.

1.11 Status byte and service request (SRQ)

Service request is controlled by two 8-bit registers: the status byte register and
the service request enable register.
Status byte register
The summary messages from the status registers and queues are used to set
or clear the appropriate bits (B2, B3, B4, B5, and B7) of the status byte
register.These bits do not latch, and their states (0 or 1) are solely dependent
on the summary messages (0 or 1).For example, if the Standard event status
register is read, its register is cleared.As a result, its summary message will
reset to 0, which in turn will clear the ESB bit in the status byte register.Bit B6 in
the status byte register is called the MSS bit.
The Master Summary Status (MSS) bit, sent in response to the *STB?indicates
the enable status of the set bit.The Request for Service (RQS) bit, sent in
response to a serial poll, indicates which device was requesting service by
pulling on the SRQ line.
For a description of the other bits in the status byte register, see STB?
When reading the status byte register using the *STB? command, bit B6 is
called the MSS bit.None of the bits in the status byte register are cleared when
using the *STB? command to read them.
The IEEE-488.1 standard has a serial poll sequence that also reads the status
byte register and is better suited to detect a service request (SRQ).When using
the serial poll, bit B6 is called the RQS bit.Serial polling causes bit B6 (RQS) to
reset.Serial polling is discussed in more detail later.
Any of the following operations clear all bits of the status byte register:
Output Queue - used to hold reading and response messages
Error Queue - used to hold error and status messages
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