Motorola MVME147 Installation And Use Manual page 92

Programming
Bit 3
4
Note
Bit 4
Bit 5
Note
Bit 6
Bit 7
4-42
The MASUAT bit allows software to conÞgure the master to
provide the UAT data transfer capability. Setting the MASUAT
bit to 1 conÞgures the master to execute unaligned VMEbus
cycles when necessary.
If the bit is cleared, the MC68030 is acknowledged so as to break
the unaligned transfer into multiple aligned cycles. This bit is
cleared by SYSRESET.
While making it optional for the master to provide the
UAT data transfer capability, the VMEbus
specification requires that all D32 slaves support it.
This bit is cleared by SYSRESET. It should remain cleared.
Setting the MASWP bit speeds up MC68030 writes to the
VMEbus. However, it should be used with caution. When
MASWP (Master Write Posting) is set, MC68030 write cycles to
the VMEbus are acknowledged by the VMEchip, before they
have actually Þnished on the VMEbus. The VMEchip Þnishes
the write cycles on its own, allowing the MC68030 to continue
with new cycles. If the SLVEN bit is cleared (slave disabled), the
VMEchip acknowledges VME writes even before it has obtained
VMEbus mastership. If the SLVEN bit is set, then it waits until it
has obtained VMEbus mastership. This bit is cleared by
SYSRESET.
The MC68030 is not notified via BERR* if an error
occurs while the VMEchip is finishing a write posted
cycle. The VMEchip can be programmed to interrupt
the MC68030 if such an event occurs (WPERREN bit in
the Utility Interrupt Mask Register). Keep in mind that
interrupt notification could be well after the occurrence
of the error.
020 - This bit should always be cleared.
DDTACK - This bit should always be cleared for 25 MHz boards
and set for 32 MHz boards.