Motorola MVME147 Installation And Use Manual page 102

Programming
Utility Interrupt Vector Register
ADDRESS
FFFE2013
4
Notes
Bits 0-2
Bits 3-7
4-52
BIT 7 BIT 6 BIT 5
UVB7 UVB6 UVB5
R/W R/W R/W
The utility interrupt vector register provides the local
CPU with a unique vector for each of the utility
interrupts. Close examination reveals that the assigned
level of each of the utility interrupts, as defined in the
Utility Interrupt Mask Register section in this chapter, is
the same as its assigned ID. This is implemented by
reflecting the state of the address lines A01-A03, that
the local CPU drives when it acknowledges an
interrupt, onto bits 0-2 of the utility vector register.
When accessing this register in the course of a normal
CPU read cycle, bit 0-2 yields the register offset value
(which is %xxxxx001).
The contents of the utility interrupt vector register
must not be changed while one of the utility interrupts
is active.
The lower three bits of the utility interrupt vector register are
encoded by the VMEchip to uniquely identify the function that
caused the utility interrupt request as shown in Table 4-7.
UVB3 through UVB7 are utility vector base bits.
The upper Þve bits of the register are programmable by
software to provide a unique base for the vector provided in the
course of acknowledging one of the utility interrupts. These bits
are cleared by any reset.
BIT 4 BIT 3 BIT 2
UVB4 UVB3 UID2
R/W R/W R
BIT 1 BIT 0
UID1 UID0
R R