Motorola MVME147 Installation And Use Manual page 66

Programming
DMA Control and Status Register
ADDRESS
FFFE1021 DONE
4
Note
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
4-16
BIT 7 BIT 6 BIT 5
8BitEr TblSizEr DMABEr TWBEr MS/SM*
R R R
All bits are cleared by reset.
When this bit is low, the DMA controller is disabled and status
bits 3-7 are reset. When this bit is high, the DMA controller is
enabled.
This bit controls the mode of the DMA controller. When this bit
is low, the DMA controller uses the address and byte count in
the address and byte count registers. When this bit is high, the
DMA controller uses address and byte counts in a table pointed
to by the table address register.
This bit controls the direction the data is transferred. When this
bit is low, the DMA controller transfers data from the SCSI bus.
When this bit is high, the DMA controller transfers data to the
SCSI bus.
This bit is set if a bus error occurred while the DMA controller
was accessing the address table. This bit is reset when the DMA
controller is disabled.
This bit is set if a bus error occurred while the DMA controller
was transferring data. This bit is reset when the DMA controller
is disabled.
This bit is set if the DMA controller accesses a table entry that is
not located in 32-bit memory. This bit is reset when the DMA
controller is disabled.
This bit (8-bit error) is set if the DMA controller receives a
handshake indicating the port was 8 bits. This bit is reset when
the DMA controller is disabled.
This bit is set when the DMA controller has stopped because all
the data has been transferred or an error has occurred. This bit is
reset when the DMA controller is disabled.
BIT 4 BIT 3 BIT 2
R R R/W
BIT 1 BIT 0
TW Enable
R/W R/W