Motorola MVME147 Installation And Use Manual page 69

Abort Interrupt Control Register
ADDRESS BIT 7
FFFE1024 IntStat
R/C
Note
Bit 3
Bit 6
Bit 7
Programming the Peripheral Channel Controller
BIT 6 BIT 5 BIT 4
Abort
R
Bit set and clear instructions should not be used on this
control register. Because the interrupt is cleared by
writing a 1 to the status bit and the status bit is a 1 to
indicate a pending interrupt, the read-modify-write
sequence may clear a pending interrupt.
When this bit is high, the interrupt is enabled. The interrupt is
disabled when this bit is low. This bit is cleared by reset.
This bit indicates the current state of the ABORT switch. When
this bit is low, the ABORT switch is not pressed. When this bit is
high, the ABORT switch is pressed.
When this bit is high, an abort interrupt is being generated at
Level 7. This bit is edge sensitive and it is set on the leading
edge of interrupt enable and abort. This bit is cleared when a 1
is written to it or when the interrupt is disabled. When cleared,
it remains cleared until the next leading edge of interrupt enable
and abort. This bit is cleared by reset.
BIT 3 BIT 2 BIT 1
Enable
R/W
BIT 0
4
4-19